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INTRODUCTION / HISTORY
(Building-up Advanced CMOS IC Design Capability)
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UMChip (1.2µm CMOS), the first microelectronics integrated circuit designed in Macau in 1993, opened up a high-tech research field in University of Macau over the past decade. Ten master students finished the UMChip as their course project by using only the software tools donated from Technical University of Lisbon. |
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A
decade passes, a groundbreaking research work – A Switched-Capacitor Bandpass Interpolating Filter (0.35µm CMOS) – was
reported in ISSCC’02, which is renowned as the “Chip Olympic”. One year later, the Analog and Mixed Signal VLSI Lab was co-founded by Prof. Rui Martins and Prof. Seng-Pan U (Ben) in September of 2003, which is currently financial supported by Research Committee of University of Macau. |
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1st
Silicon of Analog and
Mixed-Signal VLSI Lab – A Low-Voltage Low-Power
Analog-Baseband IC (0.35µm CMOS) – was reported partly in CICC'05 and
partly in VLSI'06. It marks the lowest voltage (1V) PGA and
lowest-voltage analog-baseband solution for 802.11 a/b/g WLAN up till
now and discloses two innovative techniques that will be registered as
US patents. |
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2nd
Chip of the Lab, also the 1st truly Mixed-Signal IC that was designed
and measured successfully in Macau - A 1.2-V, 10-b,
60-360MS/s Power/Speed Scalable Time-Interleaved Pipelined
Analog-to-Digital Converter (0.18µm CMOS). This work presented the
simultaneous lowest-voltage and highest-speed ADC in 0.18µm CMOS technology and has utilized several advanced low-voltage circuit
techniques to tackle with the various low-voltage design challenges. |
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The 3rd Chip of the Lab,
also the 1st using the very advanced nanometer CMOS Technology in
University of Macau - A
High-speed High-resolution Low-power Two-step Analog-to-Digital
Converter (90nm CMOS).
The ADC is constructed by novel architecture that exploits the
advantages of dynamic circuit entirely, achieving very high speed and
power efficiency. |
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The 4th Chip of the Lab is a 90-nm CMOS High-Voltage-Enabled Variable-Gain RF Front-End. Using thin-oxide devices only, this work achieves competitive performances with low power consumption in comparing with the state-of-the-art. |
The 5th Chip of the Lab is also using the 90-nm CMOS Technology in the University of Macau - A Power-Efficient 1.2V 12-bit 80MHz Reference-Ladder Free SAR ADC. A novel circuit technique has been used to remove the static power consumption from the reference ladder, thus speeding up the conversion and realizing power efficiency of the ADC. |
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