Publications

Patents
  1. , “比較器循環再用式二進位搜索型模擬數字轉換器,” 中國專利, 2011年即將申請
  2. , “以反相器為基礎架構之逐次逼進式模擬數字轉換器,” 中國專利, 2011年即將申請
  3. U-Fat Chio, He-Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “Flash-SAR Two-Step Subranging ADC,” to be submitted for US Patent Application, 2009 / 2010.
  4. Sai-Weng Sin, Seng-Pan U and R. P. Martins, “Low-Voltage Finite-Gain Compensation Technique for High-Speed Reset- and Switched-Opamp Circuits,” US Patent Application, 2009.
  5. Sai-Weng Sin, Seng-Pan U and R. P. Martins, “Very Low-Voltage SC-CMFB Technique for Fully-Differential Reset-Opamp Circuits,” US Patent Application , 2009.
  6. Pui-In Mak, Seng-Pan U and R.P.Martins, “Switched Current-Resistor Programmable Gain Array for Low-Voltage Wireless LAN System and Method Using the Same,” US Patent pending, Serial No. 12/355,658, 2009.
  7. Pui-In Mak, Seng-Pan U and R.P.Martins, “Two-Step Channel Selection for Wireless Transmitter Front-Ends,” US Patent pending, Serial No. 12/203,837, Dec. 2008.
  8. Pui-In Mak, Seng-Pan U and R. P. Martins, “DC-Offset Canceled Programmable Gain Array for Low-Voltage Wireless LAN System and Method Using the Same,” US Patent, No. 7,948,309, from May 24, 2011.
  9. Pui-In Mak, Seng-Pan U, R.P.Martins, “Two-Step Channel-Selection for Wireless Receiver Front-Ends” US Patent, No. 7,529,322, from May 5, 2009.
Journals
  1. Zushu Yan, Pui-In Mak and R. P. Martins, “Two-Stage Operational Amplifiers: Power-and-Area-Efficient Frequency Compensation for Driving a Wide Range of Capacitive Load,” IEEE Circuits and Systems Magazine, 2011
  2. Pui-In Mak and R. P. Martins, “High-/Mixed-Voltage RF and Analog CMOS Circuits Come of Age,” IEEE CAS Magazine, to appear soon in Q1 2011.
  3. Pui-In Mak, “Assisting the Career Development of Young Members – Examples of What IEEE CAS Society Have Recently Done,” IEEE Circuits and Systems Magazine, 2010, accepted.
  4. Pui-In Mak and R. P. Martins, “A 2×VDD-Enabled Mobile-TV RF Front-End with TV-GSM Interoperability in 1-V 90-nm CMOS,” IEEE Transactions on Microwave Theory and Techniques, vol. 58, No.7, pp.1664-1676, July 2010.
  5. U-Fat Chio, He-Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R. P. Martins and Franco Maloberti, “Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC,” IEEE Transactions on CAS – Part II: Express Briefs, vol. 57, No.8, pp.607-611, August 2010.
  6. Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P. Martins and Franco Maloberti, “A 10-bit 100-MS/s Reference-Free SAR ADC in 90nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 45, No.6, pp.1111-1121, June 2010.
  7. Ka-Fai Un, Pui-In Mak and R. P. Martins, “Analysis and Design of Open-Loop Multi-Phase Local-Oscillator Generator for Wireless Applications,” IEEE Transactions on Circuits and Systems – I: Regular Papers, vol. 57, no. 5, pp.970-981, May 2010. [Invited, Special Issue of ISCAS 2009]
  8. Yong Chen, Pui-In Mak and Yumei Zhou, “Mixed-Integrator Biquad for Continuous-Time Filters,” IET Electronics Letters, vol. 46, no. 8, pp. 561-563, Apr. 2010. [highlighted as significant result of the issue]
  9. Yong Chen, Pui-In Mak and Yumei Zhou, “Self-Tracking Charge Pump for Fast-Locking PLL,” IET Electronics Letters, vol. 46, no. 11, pp. 755-757, May 2010.
  10. Yan Zhu, U-Fat Chio, He-Gong Wei, Sai-Weng Sin, Seng-Pan U and R.P. Martins, “Linearity Analysis On A Series-Split Capacitor Array for High-Speed SAR ADCs,” in Hindawi VLSI Design, Special Issue with "Selected Papers from the Midwest Symposium on Circuits and Systems", vol. 2010, no. 1, pp. 1-8, April 2010, invited.
  11. He-Gong Wei, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “A Rapid Power-Switchable Track-and-Hold Amplifier in 90nm CMOS,” in IEEE Trans. on Circuits and System II – Express Briefs, vol. 57, no. 1, pp. 16-20, Jan 2010.
  12. Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A 1.2-V 10-bit 60-360MS/s Time-Interleaved Pipelined ADC in 0.18um CMOS with Minimized Supply Headroom,” in IET Proceedings - Circuits, Devices and Systems, vol. 4, no. 1, pp. 1-13, Jan 2010.
  13. Pui-In Mak, “Starting a New Team in Microelectronics Development – SWOT and New Initiatives,” IEEE Potentials, vol. 26, issue 6, pp. 34-36, Nov.-Dec. 2009.
  14. Pui-In Mak and R. P. Martins, “Design of an ESD-Protected Ultra-Wideband LNA in Nanoscale CMOS for Full-Band Mobile TV Tuners,” IEEE Transactions on Circuits and Systems – I: Regular Papers, Special Issue of ISCAS 2008, Invited, vol. 56, No.5, pp.933-942, May 2009.
  15. Pui-In Mak, “Explosive Growth Calls for More Mixed-Voltage Analog Integrated Circuits,” IEEE Potentials, vol. 26, issue 2, pp. 35-36, Mar.-Apr. 2009.
  16. Tuna Tarim, Martin Di Federico and Pui-In Mak, “Circuits and Systems Education: Viewpoint of GOLD and Industry,” IEEE Circuits and Systems Magazine, Special Issue on Circuits and Systems Education, Vol. 9, Issue 1, pp. 42-48, Mar. 2009.
  17. Chon-Teng Ma, Pui-In Mak, Mang-I Vai, Peng-Un Mak, Sio-Hang Pun, Wan Feng and R. P. Martins, “Frequency-Bandwidth-Tunable Powerline Notch Filter for Biopotential Acquisition Systems,” IET Electronics Letters, vol.45, No.4, pp.197-198, 12 February 2009.
  18. Sai-Weng Sin, Seng-Pan U, and R.P.Martins, “Generalized Circuit Techniques for Low-Voltage High-Speed Reset- and Switched-Opamps,” in IEEE Transactions on Circuits and Systems I - Regular Papers, vol. 55, no. 8, Sep 2008.
  19. Sai-Weng Sin, U-Fat Chio, Seng-Pan U and R. P. Martins, “Statistical Spectra and Distortion Analysis of Time-Interleaved Sampling Bandwidth Mismatch,” in IEEE Trans. on Circuits and Systems II – Express Briefs, vol. 55, no. 7, pp. 648 – 652, Jul 2008.
  20. Pui-In Mak, Seng-Pan U and R. P. Martins, "On the Design of Programmable-Gain Amplifier with Built-in Compact DC-Offset Cancellers for Very Low-Voltage WLAN Systems," IEEE Transactions on Circuits and Systems – I: Regular Papers, vol. 55, no. 3, March, 2008.
  21. Pui-In Mak, Seng-Pan U and R. P. Martins, “An Experimental 1-V Flexible-IF CMOS Analogue-Baseband Chain for IEEE 802.11a/b/g WLAN Receivers,” IET Proceedings - Circuits, Devices and Systems, vol. 1, no. 6, pp. 415-426, Dec. 2007.
  22. Pui-In Mak, Seng-Pan U and R. P. Martins, "Transceiver Architecture Selection - Review, State-of-the-Art Survey and Case Study," IEEE Circuits and Systems Magazine, Vol. 7, Issue 2, pp. 6-25, Jun. 2007.
  23. Pui-In Mak, Seng-Pan U and R.P.Martins, “Two-Step Channel Selection – A Novel Technique for Reconfigurable Multistandard Transceiver Front-Ends,” IEEE Transactions on Circuits and Systems-I, Regular Paper, vol.52, pp.1302-1315, Jul., 2005.
  24. Seng-Pan U, Sai-Weng Sin and R.P.Martins, “Exact Spectra Analysis of Sampled Signals with Jitter-Induced Nonuniformly Holding Effects,” IEEE Transactions on Instrumentation and Measurement, vol. 53, pp. 1279-1299, Aug. 2004.
  25. Seng-Pan U, R.P.Martins and J.E.Franca, “A 2.5-V 57-MHz 15-Tap SC Bandpass Interpolating Filter with 320-MHz Output for DDFS System in 0.35-µm CMOS,” IEEE Journal of Solid-State Circuits, vol. 39, No. 1, Jan. 2004.
  26. Pui-In Mak, Seng-Pan U and R.P.Martins, “Two-Step Channel Selection Technique by Programmable Digital-Double Quadrature Sampling for Complex Low-IF Receivers,” IEE Electronics Letters, vol. 39, no. 11, pp. 825-827, May 2003.
  27. Seng-Pan U, R.P. Martins and J.E.Franca, “Improved Switched-Capacitor Interpolators with Reduced Sample-and-Hold Effects,” IEEE Transactions on Circuits and Systems – II: Analog and Digital Signal Processing, vol.47, No.8, pp.665-684, Aug. 2000.
  28. Seng-Pan U, R.P.Martins and J.E.Franca, “Offset-& Gain-Compensated and Mismatch-Free SC Delay Circuit with Flexible Implementation", IEE Electronics Letters, vol. 35, No.3, pp.188-189, Feb. 4th. 1999.
  29. Seng-Pan U, R.P.Martins and J.E.Franca, “Impulse Sampled FIR Interpolation with SC Active-Delayed Block Polyphase Structures”, IEE Electronics Letters, vol. 34, No.5, pp.443-444, Mar. 5th. 1998.
  30. Seng-Pan U, R.P.Martins and J.E.Franca, “Switched-Capacitor Interpolators Without the Input Sample-and-Hold Filtering Effect”, IEE Electronics Letters, vol. 32, No.10, pp.879-881, May 9th. 1996.
Conference Papers
  1. He-Gong Wei, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R. P. Martins and F. Maloberti, “A 0.024mm2 8-bit 400 MS/s SAR ADC with 2-bit per Cycle and Resistive DAC in 65 nm CMOS,” in IEEE International Solid-State Circuit Conference (ISSCC), pp.187-189, Feb 2011.
  2. Pui-In Mak and R. P. Martins, “A 0.46mm2 4-dB NF Unified Receiver Front-End for Full-Band Mobile TV in 65nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, Feb. 2011, accepted.
  3. Chio-In Ieong, Mang-I Vai, Peng-Un Mak, Pui-In Mak, “ECG Heart Beat Detection Via Mathematical Morphology and Quadratic Spline Wavelet Transform,” IEEE International Conference on Consumer Electronics (ICCE), Jan. 2011, accepted.
  4. Chi Man Wong, Boyu Wang, Feng Wan, Peng Un Mak, Pui-In Mak, and Mang I Vai, “An Improved Phase-Tagged Stimuli Generation Method in Steady-State Visual Evoked Potential Based Brain-Computer Interface,” International Conference on Biomedical Engineering and Informatics (BMEI), 2010, accepted.
  5. Boyu Wang, Chi Man Wong, Feng Wan, Peng Un Mak, Pui-In Mak, and Mang I Vai, “Gaussian Mixture Model Based on Genetic Algorithm for Brain-Computer Interfaces,” International Conference on Biomedical Engineering and Informatics (BMEI), 2010, accepted.
  6. Yang Jiang, Kim-Fai Wong, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “A Return-to-Zero Feedback Technique with Reduced Clock-Jitter Sensitivity in CT ΣΔ Modulator,” to appear in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), Dec, 2010.
  7. Guohe Yin, U-Fat Chio, He-Gong Wei, Sai-Weng Sin, Seng-Pan U, R.P. Martins, Zhihua Wang, “An Ultra Low Power 9-bit 1-MS/s Pipelined SAR ADC for Bio-medical Applications,” to appear in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), Dec, 2010.
  8. Yang Jiang, Kim-Fai Wong, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “A Reduced Jitter-Sensitivity Clock Generation Technique for Continuous-Time ΣΔ Modulators,” to appear in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), Dec. 2010.
  9. Li Ding, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “An Efficient DAC and Interstage Gain Error Calibration Technique For Multi-Bit Pipelined ADCs,” to appear in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), Dec. 2010.
  10. He-Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A Process-insensitive Current-Controlled Delay Generator with Threshold Voltage Compensation,” Proc. IEEE Asian Solid-State Circuits Conference – ASSCC 2010, pp. - , Beijing, China, November 2010.
  11. Boyu Wang, Chiman Wong, Feng Wan, Peng Un Mak, Pui-In Mak, and Mang I Vai, “Trial Pruning for Classification of Single-Trial EEG Data during Motor Imagery,” International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2010, accepted.
  12. Yuan Fei, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “A Digital Background Nonlinearity Calibration Algorithm for Pipelined ADCs,” IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), 2010, accepted.
  13. Tan-Tan Zhang, Jin-Tao Li, Pui-In Mak, Mang-I Vai, Peng-Un Mak, Sio-Hang Pun, Wan Feng and R. P. Martins, “A 28-µW EEG Readout Front-End Utilizing a Current-Mode Instrumentation Amplifier and a Source-Follower-Based LPF,” IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), 2010, accepted.
  14. Chon-Teng Ma, Pui-In Mak, Mang-I Vai, Peng-Un Mak, Sio-Hang Pun, Wan Feng and R. P. Martins, “A Novel Response-Translating Lowpass Filter Achieving 1.4-to-15-Hz Tunable Cutoff for Biopotential Acquisition Systems,” IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), 2010, accepted.
  15. Pui-In Mak, “Biopotential-Readout Analog Circuits – Recent Advances and Remaining Challenges,” Regional Biomedical Engineering Society Conference, pp. 53, Sept. 2010.
  16. Sai-Weng Sin, Li Ding, Yan Zhu, He-Gong Wei, Chi-Hang Chan, U-Fat Chio, Seng-Pan U, R.P.Martins, F.Maloberti, “An 11b 60MS/S 2.1mW Two-Step Time-Interleaved SAR-ADC with Reused S&H,” in Proc. IEEE European Solid-State Circuits Conference – ESSCIRC 2010, Seville, Spain, Sept 2010.
  17. Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A Threshold-Embedded Offset Calibration Technique for Inverter-Based Flash ADCs,” in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010, pp. 489-492, Aug. 2010.
  18. Kim-Fai Wong, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “Level-Shifting Variable Current Charging Technique for High-Speed Comparator-Based Switched-Capacitor Circuits,” Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010, pp. 566-569, Aug. 2010.
  19. Si-Seng Wong, U-Fat Chio, Hou-Lon Choi, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A Power Effective 5-bit 600 MS/s Binary-Search ADC with Simplified Switching,” in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010, pp. 29-32, Aug. 2010.
  20. Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “Parasitics Nonlinearity Cancellation Technique for Split DAC Architecture by Using Capacitive Charge-Pump,” in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010, pp. 889-892, Aug. 2010.
  21. Li Ding, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A Background Amplifier Offset Calibration Technique for High-Resolution Pipelined ADC,” to appear soon in Proc. IEEE International NEWCAS Conference – NEWCAS 2010, Montréal, Canada, June 2010.
  22. Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, “A Voltage Feedback Charge Compensation Technique for Split DAC Architecture in SAR ADCs,” Proc. IEEE International Symposium on Circuits and Systems – ISCAS 2010, pp.4061-4064 , Paris, France, May-June 2010.
  23. Miguel A. Martins, Ka-Fai Un, Pui-In Mak and R. P. Martins, “Differential SC Biquad Filter with Hybrid Utilization of OpAmp and Comparator-Based Circuit,” Proc. IEEE International Symposium on Circuits and Systems – ISCAS 2010, pp.1276-1279, Paris, France, May-June 2010.
  24. Yong Chen, Pui-In Mak and Yumei Zhou, “Source-Follower-Based Biquad Cell for Continuous-Time Zero-Pole Type Filters,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3629-3632, May 2010.
  25. Li Ding, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A Noise-Insensitive Offset Calibration Technique for Time Interleaved SAR ADC,” Proc. IEEE International Symposium on Circuits and Systems – LASCAS 2010, Iguaçu Falls, Brazil, February 2010.
  26. Boyu Wang, Feng Wan, Peng Un Mak, Pui-In Mak, and Mang I Vai, “EEG Signals Classification for Brain Computer Interfaces Based on Gaussian Process Classifier,” in Proc. of International Conference on Information, Communications and Signal Processing (ICICS)), pp. 1-5, Dec. 2009.
  27. Sai-Weng Sin, He-Gong Wei, U-Fat Chio, Yan Zhu, Seng-Pan U, R.P. Martins and Franco Maloberti, “On-Chip Small Capacitor Mismatches Measurement Technique using Beta-Multiplier-Biased Ring Oscillator,” in Proc. of 2009 IEEE Asian Solid-State Circuit Conference (A-SSCC), pp. 49-52, Nov 2009.
  28. Jin Tao Li, Sio Hang Pun, Mang I Vai, Peng Un Mak, Pui-In Mak and Feng Wan, “Design Considerations of Current Mode Instrumentation Amplifier for Portable Biosignal Acquisition System,” in Proc. of IEEE Biomedical Circuits and Systems Conference (BIOCAS), pp 9-12, Nov. 2009.
  29. Si-Seng Wong, Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “Parasitic Calibration by Two-Step Ratio Approaching Techinque for Split Capacitor Array SAR ADCs,” in Proc. of 2009 International SoC Design Conference (ISOCC), invited, pp. 333-336, Nov. 2009.
  30. Chi-Hang Chan, Yan Zhu, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A Voltage-Controlled Capacitance Offset Calibration Technique for High Resolution Dynamic Comparator,” in Proc. of 2009 International SoC Design Conference (ISOCC), invited, pp. 392-395, Nov. 2009.
  31. Cheok-Teng Lei, Seng-Pan U and R. P. Martins, “High-Speed Robust Level Converter for Ultra-Low Power 0.6-V LSIs to 3.3-V I/O,” in Proc. of 2009 International SoC Design Conference (ISOCC), invited, pp. 396-399, Nov. 2009.
  32. Chang-Hao Chen, Pui-In Mak, Tan-Tan Zhang, Mang-I Vai, Peng-Un Mak, Sio-Hang Pun, Wan Feng and R. P. Martins, “A 2.4 Hz-to-10 kHz-Tunable Biopotential Filter Using a Novel Capacitor Multiplier,” IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia), pp. 372-375, Nov. 2009.
  33. Keng-Wai Lo, Pui-In Mak and R. P. Martins, “An Active-Balun LNA with Forestage-Poststage Gain Controls for VHF/UHF Mobile-TV Tuners,” IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia), pp. 165-168, Nov. 2009.
  34. U-Fat Chio, Hou-Lon Choi, Chi-Hang Chan, Si-Seng Wong, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “Comparator-Based Successive Folding ADC,” IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia), pp. 117-120, Nov. 2009.
  35. Kim-Fai Wong, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “A Modified Charging Algorithm for Comparator-Based Switched-Capacitor Circuits,” in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2009, pp.86-89, Cancun, Mexico, August 2009.
  36. Boyu Wang, Chi Man Wong, Feng Wan, Peng Un Mak, Pui-In Mak, and Mang I Vai, “Comparison of Different Classification Methods for EEG-Based Brain Computer Interfaces: A Case Study,” in Proc. of International Conference on Information and Automation (ICIA), pp. 1416-1421, Jun. 2009.
  37. Pui-In Mak and R. P. Martins, “2×VDD–Enabled TV-Tuner RF Front-End Supporting TV-GSM Interoperation in 90nm CMOS,” in IEEE Symposium on VLSI Circuits (VLSI), Digest of Technical Papers, pp. 278-279, Jun. 2009.
  38. Ka-Fai Un, Pui-In Mak and R. P. Martins, “An Open-Loop Multiphase (360o-div-by-8) Local Oscillator Generator with High-Precision Correlated Phases for Mobile-TV Tuners,” Proc. IEEE International Symposium on Circuits and Systems – ISCAS 2009, pp. 433-436, Taipei, Taiwan, May 2009.
  39. Chon-Teng Ma, Pui-In Mak, Mang-I Vai, Peng-Un Mak, Sio-Hang Pun, Feng Wan and R. P. Martins, “A 90nm CMOS Bio-Potential Signals Readout Front-End Utilizing a Novel Chopper Notch Filter for Powerline Interference Rejection,” Proc. IEEE International Symposium on Circuits and Systems – ISCAS 2009, pp. 665-668, Taipei, Taiwan, May 2009.
  40. Li Ding, Sio Chan, Kim-Fai Wong, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “A Pseudo-Differential Comparator-Based Pipelined ADC with Common Mode Feedforward Technique,” in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 276-279, Dec. 2008.
  41. Ngai Kong, Seng-Pan U and R. P. Martins, “Novel CMOS Switched-Current Mode Sequential Shift Forward Inference Circuit for Fuzzy Logic Controller,” in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 396-399, Dec. 2008.
  42. Kim Fai Wong, Ka Ian Lei, Seng-Pan U and R. P. Martins, “1-V 90dB DR Audio Stereo DAC with Embedding Headphone Driver” in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 1160-1163, Dec. 2008.
  43. U Fat Chio, Hegong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “A Self-Timing Switch-Driving Register by Precharge-Evaluate Logic for High-Speed SAR ADCs,” in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 1164-1167, Dec. 2008.
  44. Hegong Wei, U Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “A Process- and Temperature- Insensitive Current-Controlled Delay Generator for Sampled-Data Systems,” in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 1192-1195, Dec. 2008.
  45. Ka-Fai Un, Pui-In Mak and R. P. Martins, “A DC-Offset-Compensated, CT/DT Hybrid Filter with Process-Insensitive Cutoff and Low In-Band Group-Delay Variation for WLAN Receivers,” in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS) , pp. 1360-1363, Dec. 2008.
  46. Yan Zhu, U Fat Chio, Hegong Wei, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “A Power-Efficient Capacitor Structure for High-Speed Charge Recycling SAR ADCs,” in Proceedings of IEEE International Conference on Electronics, Circuits, and Systems - ICECS 2008.
  47. Yan Zhu, U Fat Chio, Hegong Wei, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs,” in Proceedings of IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2008, Knoxville, USA.
  48. Chon-Teng Ma, Pui-In Mak, Vai-Mang I, Peng-Un Mak, Sio-Hang Pun and R. P. Martins, “Design of a Low-Power Low-Noise Bio-Potential Readout Front-End in CMOS,” in Proc. of Regional Inter-University Graduate Conference on Electrical Engineering (RIUGCEE) , Xi’an, China, July 2008.
  49. Pui-In Mak, Ka-Hou Ao Ieong and R. P. Martins, “An Open-Source-Input, Ultra- Wideband LNA with Mixed-Voltage ESD Protection for Full-Band (170-to-1700 MHz) Mobile TV Tuners,” in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS) , pp. 668-671, May 2008.
  50. Pui-In Mak, “Views, Experience, and Prospects for Education in Circuits and Systems,” in Proc. of the IEEE Circuits and Systems Society Education Workshop , p. 9, May 22, 2008.
  51. He-Gong Wei, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U and R.P. Martins, “A Power Scalable 6-bit 1.2GS/s Flash ADC with Power on/off Track-and-Hold and Preamplifier,” in Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 5-8, Seattle, USA, May 2008.
  52. Ngai Kong, Seng-Pan U and R.P. Martins, “A Novel Reconfigurable Membership Function Circuit for Analog Fuzzy Logic Controller,” Proceedings of 20th China Symposium on Circuits and Systems – CSCAS 2007, Guangzhou, China.
  53. He-Gong Wei, Chon-Kit Lai, Seng-Pan U and R.P. Martins, “A 100MS/s Recycling 2-Step ADC Embedding Programmable Gain Amplification for DVB Satellite,” in Proc. of the 50th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 132-135, Montreal, Canada, Aug. 2007.
  54. Weng-Ieng Mok, Pui-In Mak, Seng-Pan U and R. P. Martins, "Highly-Linear Successive-Approximation Front-End Digitizer with Built-in Sample-and-Hold Function for Pipeline/Two-Step ADC," in Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1947-1950, New Orleans, USA, May 2007.
  55. Ka-Hou Ao Ieong, Seng-Pan U and R.P. Martins, "A 1-V 2.5-mW Transient-Improved Current-Steering DAC using Charge-Removal-Replacement Technique," in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 183-186, Dec. 2006.
  56. Pui-In Mak, Seng-Pan U and R. P. Martins, “A 1V 14mW-per-Channel Flexible-IF CMOS Analog-Baseband IC for 802.11a/b/g Receivers,” in IEEE Symposium on VLSI Circuits (VLSI), Digest of Technical Papers, pp.288-289, Jun. 2006.
  57. Ka-Hou Ao Ieong, Seng-Pan U, R.P.Martins, “Design of a 1-V 10-bit 120MS/s Current-Steering DAC with Transient-Improved Technique,” Proc. IEEE/IEE Regional Inter-University Post-graduate EEE Conference – RIUPEEEC 2006, pp.137-140, Macao, China, July 2006
  58. Sai-Weng Sin, Seng-Pan U, R.P.Martins, “Novel Timing-Skew-Insensitive, Multi-phase Clock Generation Scheme for Parallel DAC and N-Path Filter,” Proc. IEEE/IEE Regional Inter-University Post-graduate EEE Conference – RIUPEEEC 2006, pp.133-136, Macao, China, July 2006
  59. Weng-Ieng Mok, Pui-In Mak, Seng-Pan U and R. P. Martins, “A Novel Architecture of Comparator-Mismatch-Free Multi-bit Pipeline ADC,” Proceedings of the Regional Inter-University Postgraduate Electrical and Electronic Engineering Conference (RIUPEEEC), Session of Circuit and System I, pp.129-132, Macao, China, July 2006.
  60. Chon In Lao, Seng-Pan U, R.P.Martins, “An Expandable and Extendable High-Order Semi-MASH Sigma Delta Modulator,” Proc. IEEE/IEE Regional Inter-University Post-graduate EEE Conference – RIUPEEEC 2006, pp.68-73, Macao, China, July 2006.
  61. Ngai Kong, Seng-Pan U, R.P.Martins, “A Novel Current-Mode Reconfigurable Membership Function Circuit for Mixed-Signal Fuzzy Hardware,” Proc. IEEE/IEE Regional Inter-University Post-graduate EEE Conference – RIUPEEEC 2006, pp.101-104, Macao, China, July 2006.
  62. Pui-In Mak, Seng-Pan U, R.P.Martins, “Design and Test Strategy underlying a Low-Voltage Analog-Baseband IC for 802.11a/b/g WLAN SiP Receivers,” in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2473-2479, May 2006.
  63. Chon-In Lao, Seng-Pan U, R.P.Martins, “A Novel Effective Band-pass Semi-MASH Sigma-Delta Modulator with Double-Sampling Mismatch-Free Resonator,” in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 581- 584, Kos, Greece, May 2006.
  64. Kin-Sang Chio, Seng-Pan U, R.P.Martins, “A Dual-Mode Low-Distortion Sigma-Delta Modulator with Relaxing Quantization Level,” in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp.1892-1895, Kos, Greece, May 2006.
  65. Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A Novel Low-Voltage Finite-Gain Compensation Technique for High-Speed Reset- and Switched-Opamp Circuits,” in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp.3794-3797, Kos, Greece, May 2006.
  66. Jun-Xia Ma, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A Power-Efficient 1.056 GS/s Resolution-Switchable 5-bit/6-bit Flash ADC for UWB Applications,” in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp.4305-4308, Kos, Greece, May 2006.
  67. Pui-In Mak, Seng-Pan U, R. P. Martins, “A 1V IEEE 802.11a/b/g-Compliant Receiver IF-to-Baseband Chip in 0.35µm CMOS for Low-Cost Wireless SiP,” Proceedings of 52nd Edition ISSCC, San Francisco, USA, and 42nd Edition DAC, Anaheim, California, USA..
  68. Pui-In Mak, Seng-Pan U, R. P. Martins, “A 1-V Transient-Free and DC-Offset-Canceled PGA with a 17.1-MHz Constant Bandwidth over 52-dB Control Range in 0.35-µm CMOS,” in Proc. of IEEE Custom Integrated Circuits Conference (CICC), pp. 649-652, USA, Sep. 2005.
  69. Pui-In Mak, Seng-Pan U, R. P. Martins, “Multistandard-Compliant Receiver Architecture with low-voltage Implementation,” in Proc. of Ph.D. Research In Micro-Electronics & Electronics (PRIME), pp. 223-226, Lausanne, Switzerland, Jul. 2005.
  70. Sai-Weng Sin, Seng-Pan U, R. P. Martins, “Novel low-voltage circuit techniques for fully-differential reset- and switched-opamps,” in Proc. of Ph.D. Research In Micro-Electronics & Electronics (PRIME), Switzerland, pp. 398-401, Lausanne, Switzerland, Jul. 2005.
  71. Weng-Ieng Mok, Pui-In Mak, Seng-Pan U, R. P. Martins, “On-Chip Unsteady Reference Voltage Compensation Techniques for Very-High-Speed Pipelined ADC,” in Proc. of Regional Inter-University Postgraduate Electrical and Electronic Engineering Conference (RIUPEEEC), pp. 276-280, Hong Kong, China, Jun. 2005.
  72. Sai-Weng Sin, Seng-Pan U and R.P.Martins, "A Novel Low-Voltage Cross-Coupled Passive Sampling Branch for Reset- and Switched-Opamp Circuits," in Proc.of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1585-1588, Kobe, Japan, May 2005
  73. Ka-Hou Ao Ieong, Chong-Yin Fok, Pui-In Mak, Seng-Pan U and R.P.Martins, “A Frequency Up-Conversion and Two-Step Channel Selection Embedded CMOS D/A Interface,” in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 392-395, Kobe, Japan, May 2005.
  74. Sai-Weng Sin, Seng-Pan U and R.P.Martins, "A Novel Very Low-Voltage SC-CMFB Technique for Fully-Differential Reset-Opamp Circuits," in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1581-1584, Kobe, Japan, May 2005.
  75. Chon-In Lao, Seng-Pan U and R.P.Martins, "A Novel Semi-MASH Sub-stage for High-order Cascade Sigma-Delta Modulators," in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3095-3098, Kobe, Japan, May 2005.
  76. Kin-Sang Chio, Seng-Pan U and R.P.Martins, "A Robust 3rd Order Low-Distortion Multi-bit Sigma-Delta Modulator with Reduced Number of Op-amp Technique for WCDMA," in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3099-3102, Kobe, Japan, May 2005.
  77. Sai-Weng Sin, Seng-Pan U and R.P.Martins, “A Generalized Timing-Skew-Free, Multi-Phase Clock Generation Platform for Parallel Sampled-Data Systems,” in Proc. of 2004 IEEE International Symposium on Circuits and Systems (ISCAS), vol.1, pp. I-369 – I-372 , May 2004.
  78. Pui-In Mak, Seng-Pan U and R.P.Martins, “A Low-IF/Zero-IF Reconfigurable Receiver with Two-Step Channel Selection Technique for Multistandard Applications,” in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp.417-420, Vancouver, Canada, May 2004.
  79. Pui-In Mak, Kin-Kwan Ma, Weng-Ieng Mok, Chi-Sam Sou, Kit-Man Ho, Cheng-Man Ng, Seng-Pan U and R.P.Martins, “An I/Q-Multiplexed and OTA-Shared CMOS Pipelined ADC with an A-DQS S/H Front-End for Two-Step-Channel-Select Low-IF Receiver,” in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp.1068-1071, Vancouver, Canada, May 2004.
  80. Pui-In Mak, Seng-Pan U and R.P.Martins, “A Power-and-Area Efficient, Multifunctional CMOS A/D Interface for a Low-IF/Zero-IF Reconfigurable Receiver,” in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS), pp. 233-238, Macau SAR, China, Oct. 2004.
  81. Pui-In Mak, Ka-Hou Ao Ieong, Chong-Yin Fok, Seng-Pan U and R.P.Martins, “A Complex Low-IF Transceiver Architecture for Relaxing Phase Noise and Settling Time Requirements of RF PLL-FS,” in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS), pp. 221-226, Macau SAR, China, Oct. 2004.
  82. Hon-Weng Chong, Kai-Yiu Che, Seng-Pan U and R.P.Martins, “A 1-V 2.56-MHz Clock-Rate CMOS Multi-bit Sigma-Delta Modulator with Reset-Opamp Technique and Pseudo Data-Wwighted-Averaging for Portable Audio Data Acquistion,” in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS), pp. 180-185, Macau SAR, China, Oct. 2004.
  83. Weng-Ieng Mok, Pui-In Mak, Seng-Pan U and R.P.Martins, “Model, Characterization and Solutions of Unstable Reference Voltage for Very-High-Speed Pipelined A/D Converters,” in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS), pp. 138-143, Macau SAR, China, Oct. 2004.
  84. Kai-Yiu Che, Hon-Weng Chong, Seng-Pan U and R.P.Martins, “A 1-V 5.12-MHz Sampling-Rate 13-bit CMOS Sigma-Delta Modulator Using Reset-Opamp Technique for Portable Aduio Data Acquistion System,” in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS), pp. 186-191, Macau SAR, China, Oct. 2004.
  85. Ka-Hou Ao Ieong, Chong-Yin Fok, Seng-Pan U and R.P.Martins, “A Multistandard Transmitter D/A Interface with Embedded Frequency Up-Conversion and Two-Step Channel Selection,” in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS), pp. 215-220, Macau SAR, China, Oct. 2004.
  86. Sai-Weng Sin, Seng-Pan U, R.P.Martins, “Novel Low Jitter Multi-Phase Clock Generation Scheme for Parallel Analog-to-Digital Conversion Systems,” Proc. IEEE/IEEJapan International Analog VLSI Workshop – AVLSIWS 2004, pp. 172-175, University of Macau, Macao, China, October 2004.
  87. Weng-Ieng Mok, Pui-In Mak, Seng-Pan U and R.P.Martins, “Modeling of Noise Sources in Reference Voltage Generator for Very-High-Speed Pipelined ADC,” in Proc. of the 47th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), vol.1 , pp. 5-8, Hiroshima, Japan, Jul. 2004.
  88. Kin-Sang Chio, Seng-Pan U and R.P.Martins,“A Novel Low-Voltage 2nd-Order Sigma-Delta Modulator with Double-Sampling for GSM/DECT/WCDMA,” in Proc. of International Conference on Communications, Circuits and Systems (ICCCAS), pp. 1146-1150, vol. 2, Jun. 2004.
  89. Pui-In Mak, Seng-Pan U and R.P.Martins, “A Front-to-Back-End Modeling of I/Q Mismatch Effects in a Complex-IF Receiver for Image-Rejection Enhancement,” in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp.631-634, Sharjah, U. A. Emirates, Dec. 2003.
  90. Pui-In Mak, Chi-Sam Sou, Seng-Pan U and R.P.Martins, “Frequency-Downconversion and IF Channel Selection A-DQS Sample-and-Hold Pair for Two-Step-Channel-Select Low-IF Receiver,” in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 479-482, Sharjah, U.A. Emirates, Dec. 2003.
  91. Pui-In Mak, Seng-Pan U and R.P.Martins, “A Programmable Switched-Capacitor A-DQS Frequency Downconverter for Two-Step Channel Selection Wireless Receiver,” in Proc.of International Conference on ASIC (ASICON), vol. 1, pp. 573-576, Beijing, China, Oct. 2003.
  92. Pui-In Mak, Weng-Ieng Mok, Seng-Pan U and R.P.Martins, “I/Q Imbalance Modeling of Quadrature Transceiver Analog Front-Ends in SIMULINK,” in Proc. of IEEE International Conference on Vehicular Technology, vol. 4, pp. 2371 – 2374, Orlando, USA, Oct. 2003.
  93. Chon-In Lao, Seng-Pan U, R.P.Martins, “Bandpass Sigma-Delta Modulator SIMULINK® Non-Idealities Model with Behavior Simulation,” Proc. International Conference on ASIC – ASICON 2003, pp. 203-206, Beijing, China, October 2003.
  94. Seng-Pan U, Sai-Weng Sin and R.P.Martins, "Spectra Analysis of Nonuniformly Holding Signals for Time-Interleaved Systems with Timing Mismatches," in Proc. of IEEE Instrumentation and Measurement Technology Conference (IMTC), Vol. 2, pp. 1298-1301, Vail, Colorado, U.S.A., May 2003.
  95. Sai-Weng Sin, Seng-Pan U, and R.P.Martins, "Timing-Mismatch Analysis in High-Speed Analog Front-End with Nonuniformly Holding Output,” in Proc. of IEEE International Symposium on Circuits and Systems 2003 (ISCAS), Vol. I, pp. 129-132, Bangkok, Thailand, May 2003.
  96. Chon-In Lao, Ho-Ieng Ieong, Kuai-Fok Au, Kuok-Hang Mok, Seng-Pan U, and R.P.Martins, "A 10.7-MHz Bandpass Sigma-Delta Modulator using Double-Delay Single-Opamp SC Resonator with Double-Sampling," in Proc. of IEEE International Symposium on Circuits and Systems 2003 (ISCAS), Vol. I, pp. 1061-1064, Bangkok, Thailand, May 2003.
  97. Sai-Weng Sin, Seng-Pan U and R.P.Martins, "Quantitative Noise Analysis of Jitter-Induced Non-Uniformly Sampled-And-Held Signals," in Proc. of IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Vol. 6, pp. VI_253-VI_256, Hong Kong, China, Apr. 2003.
  98. Pui-In Mak, Seng-Pan U and R.P.Martins, “A Novel IF Channel Selection Technique by Analog-Double quadrature Sampling for Complex Low-IF Receivers,” in Proc. of International Conference on Communication Technology (ICCT), vol. 2, pp.1238-1241, Beijing, China, Apr. 2003.
  99. Fan Lou, Seng-Pan U, R.P.Martins, “N-Path Multirate Sigma-Delta Modulator For High Frequency Application,” in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), Vol. I, pp. 315-318, Dubrovnik, Croatia, September 2002.
  100. Fan Lou, Seng-Pan U, R.P.Martins, "Mismatch-Insensitive N-Path Multirate Sigma-Delta Modulator for High-Frequency Applications," in Proc. of 45th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Vol.I, pp. I-360-I-363, Tulsa, Oklahoma, USA, August 2002.
  101. Seng-Pan U, R.P.Martins, and J.E.Franca, "Design and Analysis of Low Timing-Skew Clock Generation for Time-Interleaved Sampled-Data Systems," in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), vol. IV, pp. 441-444, Scottsdale, Arizona, U.S.A., May 2002.
  102. Seng-Pan U, R.P.Martins and J.E.Franca, “A 2.5V 57MHz 15-Tap SC Bandpass Interpolating Filter with 320MHz Output Sampling Rate in 0.35µm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, vol. 45 / No.1, pp.380-381(& 475), San Francisco, U.S.A., Feb. 2002.
  103. Seng-Pan U, R.P.Martins and J.E.Franca, “A 2.5V 57MHz 15-Tap SC Bandpass Interpolating Filter with 320MHz Output Sampling Rate in 0.35µm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, vol. 45 / No.2 (Visuals Supplement), pp.306-307(& 518-519), San Francisco, U.S.A., Feb. 2002.
  104. Seng-Pan U, Ho-Ming Cheong, Iu-Leong Chan, Keng-Meng Chan, U-Chun Chan, Mantou Liu, R.P.Martins, J.E.Franca, “An SC CCIR-601 Video Restitution Filter with 13.5 MSample/s Input and 108 MSample/s Output,” in Proc. of IEEE International Conference on ASIC (ASICON), pp.374-377, Shanghai, China, Oct. 2001.
  105. Seng-Pan U, “A Novel Frequency-Translated Filtering Technique for DDFS Systems and its Integrated Circuit Implementation,” in Proc. of The 4th China Association Science and Technology (CAST) Conference of Young Scientists, pp.46-47, Beijing, China, Oct. 2001 (in Chinese).
  106. Seng-Pan U, R.P.Martins, J.E.Franca, “A High-Speed Frequency Up-Translated SC Bandpass Filter With Auto-Zeroing For DDFS Systems,” in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), vol. I, pp.320-323, Sydney, Australia, May 2001.
  107. Seng-Pan U, R.P.Martins, J.E.Franca, “High-Frequency Low-Power Multirate SC Realizations For NTSC/PAL Digital Video Filtering,” in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), vol. I, pp.204-207, Sydney, Australia, May 2001.
  108. Seng-Pan U, R.P.Martins, J.E.Franca, “Experimental Results of SC Fractional Multirate Converters with Intermittent Polyphase Structures,” in Proc. of the First Portugal-China Workshop on Solid-State Circuits, pp.28-29, Shanghai, China. Oct. 2000.
  109. Seng-Pan U, R.P.Martins, J.E.Franca, “A Linear-Phase Halfband SC Video Interpolation Filter with Coefficient-Sharing and Gain- & Offset-Compensation,” in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), vol. III, pp.177-180, Geneva, Switzerland, May 2000.
  110. Seng-Pan U, R.P.Martins, J.E.Franca, “A 120 MHz SC 4th-Order Elliptic Interpolation Filter with Accurate Gain and Offset Compensation for Direct Digital Frequency Synthesizer,” in Proc. of The First IEEE Asia-Pacific Conference on ASICs (AP-ASIC’99), pp.1-4, Korea, Aug. 1999.
  111. Seng-Pan U, R.P.Martins, J.E.Franca, “Highly Accurate Mismatch-Free SC Delay Circuits with Reduced Finite Gain and Offset Sensitivity,” in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), vol.2, pp.57-60, USA, May 1999.
  112. Seng-Pan U, R.P.Martins, J.E.Franca, “High Performance Multirate SC Circuits with Predictive Correlated Double Sampling Technique,” in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), vol.2, pp.77-80, USA, May 1999.
  113. Seng-Pan U, R.P.Martins, J.E.Franca, “A Novel Half-Band SC Architecture for Effective Analog Impulse Sampled Interpolation,” in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp.389-403, Lisbon, Portugal, Sept. 1998.
  114. Seng-Pan U, “A Novel Impulse Sampled Interpolation Technique for Efficient and Accurate Analog Multirate Signal Processing,” in Proc. of The 3rd China Association for Science and Technology (CAST) Conference of Young Scientists, Beijing, China, Aug. 1998 (in Chinese).
  115. Seng-Pan U, R.P.Martins, J.E.Franca, “Impulse Sampled Intermittent SC FIR Rational Decimators with Double-Sampling,” in Proc. of IEEE Midwest Symposium on Circuits and Systems, pp.977-980, Sacramento, USA, Aug. 1997.
  116. Seng-Pan U, R.P.Martins, J.E.Franca, “Intermittent Polyphase SC Structures for FIR Rational Interpolation,” in Proc. of IEEE International Symposium on Circuits and Systems 1997 (ISCAS), vol.I, pp.121-124, Hong Kong, Jun. 1997.
  117. Seng-Pan U, R.P.Martins, J.E.Franca, “New Impulse Sampled IIR Switched-Capacitor Interpolators,” in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp.203-206, Rodos, Greece, Oct. 1996.
  118. Seng-Pan U, R.P.Martins, J.E.Franca, “Switched-Capacitor Finite Impulse Response Interpolators without the Input Sample-and-Hold Filtering Effect,” in Proc. of IEEE Midwest Symposium on Circuits and Systems (MWSCAS), Ames, Iowa, USA, Aug. 1996
  119. R.P.Martins, Pong Chi Wai, Seng-Pan U, et al., “UMCHIP - First Integrated Circuit designed in Macau (Multifunctional & Mixed A/D - 1.2µm CMOS),” Proc. Int. Conf. on Education, Practice & Promotion of Computational Methods in Engineering using Small Computers - EPMESC-V, pp.1583-1589, Macao, August 1995.
 


Department of Electrical and Electronics Engineering
Faculty of Science and Technology
University of Macau

Last Modified: 18/03/2010