Seng Pan U, Ben  余成斌
Visiting Professor

Academic Qualifications | Professional Experience | Honors and Awards | Student Honors and Awards under Advisory | Professional Services - Professional Associations and Institutions | Professional Services - Technical Committee and Conferences | Professional Activities | Invited Speeches & Technical Talks | Professional Affiliations | Teaching Experience | Thesis Supervision | Research Specialty | R&D Project Management Experience | Scientific Publications | Contact Details

Academic Qualifications
Professional Experience

Academic Working Experience

Industrial Working Experience


Honors and Awards

2013 “2012 Outstanding Chapter Award” (Recipient as the Chapter Chair) awarded from IEEE Solid-State Circuits Society
2012 Second Class Award of the Macao Science and Technology Awards - Science and Technology Progress Award澳門科學技術獎勵科技進步獎二等獎(第一完成人),
awarded from Science and Technology Development Fund of Macao SAR (FDCT).
2012 Second Class Award of the Macao Science and Technology Awards - Technological Invention Award澳門科學技術獎勵技術發明獎二等獎(第二完成人),
awarded from Science and Technology Development Fund of Macao SAR (FDCT).
2011Second Class Award of the State Scientific and Technological Progress Award 國家科學技術進步獎二等獎 (第一完成人) (澳門首獲 First from Macau)
The State Science and Technology Prizes (國家科學技術獎励) is the highest honor in China in science and technology, in order to recognize citizens and organizations who have made remarkable contributions to scientific and technological progress, and to promote the development of science and technology.
2010 Honorary Title of Value of 2010”, awarded by Macau SAR Government.
An annual government decoration for Macau citizen who has great contribution to Macau SAR reputation, development and society advancement.
2010 “HLHL Scientific and Technological Innovation Award” 何梁何利基金科學與技術創新獎 (澳門首獲 First from Macau) awarded from He Leung Ho Lee Foundation.
HLHL Scientific and Technology Prize is the highest level non-government annual award for its impact factor and authority in China science and technology society. The innovation award is to reward outstanding individuals who have attained remarkable R&D achievements in science and technology, have created businesses or famous brands with proprietary intellectual property through technology and management innovation, and thus have created enormous economic and social benefits for society.
2009 “IEEE CAS Chapter-of-the-Year Award” (Co-Recipient as Vice Chair of the Chapter) awarded from IEEE Circuits and Systems Society
2005 “Lecture Fellowship” awarded from K. C. Wong Education Foundation
2005 Nomination of “The 2005 National Best Doctoral Dissertations” from the Ministry of Education and State Academic Degrees Committee of the State Council.
2004 “FST Teaching Award 2004” awarded from University of Macau
2003 “Young Researcher Prize 2003” awarded from International Institute of Macau
2003 “The Most Favorite Teacher in 1st- and 2nd-year of EEE” awarded from Faculty of Science and Technology Students’ Association
2003 “The Most Favorite Teacher in 3rd- and 4th-year of EEE” awarded from Faculty of Science and Technology Students’ Association
2003 “The 2003 Chinese Expertise Dictionary” China.
2002 “The Most Favorite Teacher in EEE” awarded from Faculty of Science and Technology Students’ Association
2002 “Very Good with Honor and Distinction” awarded from University of Macau for Ph.D. degree (Highest honor)
2002 “The Outstanding Alumni Award” awarded from Hou Kong Middle School of Macau
2001 “Excellent Young Scholar Award 2001 (First Prize)” awarded from University of Macau.
2000 “Excellent Research Scholarship” from Center of Microsystems, Instituto Superior Técnico (IST), Universidade Técnica de Lisboa, Portugal
1999–2000 “Research Scholarship” from Fundação Oriente
1998 “Certificate of Merit” awarded from Institution of Electrical Engineers (IEE) for IEE (HK) Younger Members Section Paper Contest 97/98 (Postgraduate Session)
1998 “Certificate of Merit” awarded from Institute of Electrical and Electronic Engineers (IEEE) for 1998 IEEE Postgraduate Student Paper Contest (HK)
1997 “Very Good with Honor and Distinction” awarded from University of Macau for postgraduate study (Highest honor)
1991 “Excellent University Graduate Award” from Jinan University
1989–1991 “Excellent Student Scholarship” from Macau Higher Education Foundation
1987–1991 “Outstanding Student Scholarship” from Jinan University every semester
1990 “Province Outstanding University Scholar Award” awarded from the Guangdong Return Overseas Chinese Association

Student Honors and Awards under Advisory

Graduate Research

Undergraduate Final Year Project


Professional Services - Professional Associations and Institutions
Professional Services - Technical Committee and Conferences
Professional Activities
Invited Speeches & Technical Talks

Conference or Tutorial Talks

Local Invited Speeches


Professional Affiliations
Teaching Experience

B.Sc. Courses

  1. System Design (ELEC437)
  2. Final Year Project (ELEC402)
  3. Circuit Analysis (ELEC231)
  4. Signals & Systems (ELEC261)
  5. Digital Signal Processing (ELEC370)
M.Sc. Courses
  1. Introduction to Research (IMSE001)
  2. Thesis (IMSE999)
  3. Microelectronics Circuit Design (IMSE004)
  4. Microelectronics for Telecommunication and Signal Processing (IMSE011)

Thesis Supervision

PH.D. Theses

  1. Chio U Fat (Alpha), Low-Power High-Speed ADC using Novel Two-Step Flash-SAR Architecture, 2012
  2. He-Gong Wei (Abner), Design techniques of High-Speed Low-power Small-Area Successive Approximation ADC, 2011
  3. Yan Zhu (Julia), Low-Power and High-Speed Reference-Free Successive Approximation Register ADCs, 2011
  4. Sin Sai Weng (Terry), Low-Voltage Very High-Speed Time-Interleaved Pipeline A-to-D Converter for Wideband Applications, 2007
  5. Mak Pui In (Elvis), Multistandard-Compliant and Low-Voltage Analog-Baseband Techniques for Wireless Communication Systems, 2006
  6. Arshad Hussain, The Design of Noise-Tolerant Passive Sigma-Delta ADC, On-going
  7. Zhong Jianyu (Jankey), Background Digital Calibration Techniques in Split-SAR ADC, On-going
  8. Li Ding, Digital Calibrated High-speed ADC , On-going
  9. Kim-Fai Wong (Vitor), Low Power SDM ADC, On-going
  10. Feng Da, Ultra Power Efficient Dynamic flash ADC, On-going
  11. Wong Si Seng (Dicky), Binary Search Algorithm and Digital Calibrated ADC, On-going
  12. Chan Chi Hang (Ivor), High Speed Power-Efficient Nyquist ADCs, On-going
  13. Zhongwu Zhao, High Speed Power-Efficient Nyquist ADCs, On-going

Master Theses

  1. Wong Si Seng (Dicky),Design of Analog-to-Digital Converters with Binary Search Algorithm andDigital Calibration Techniques, 2011
  2. Chan Chi Hang (Ivor), A Study on Comparator Offset Calibration Techniques and in High Speed Nyquist ADCs, 2011
  3. Li Ding,High-Performance Comparator-Based Pipelined Analog-to-Digital Converter, 2010
  4. Kim-Fai Wong,Fully-Differential Implementation of Comparator-Based Switched-Capacitor Circuits, 2010
  5. He-Gong Wei (Abner), High speed Analog-to-Digital Converter with high accurate Track-and-Hold circuit, 2008
  6. Yan Zhu (Julia), Comprehensive Linearity Analysis of High-Speed Power-Efficient Successive-Approximation ADCs with Series Capacitive DAC Structure, 2008
  7. Kin-Sang Chio (Sunny), A Robust Low-Distortion Sigma-Delta Modulator for Dual-Mode Wireless Receivers, 2007
  8. Kong Ngai (Nelson),Reconfigurable Switched-Current Fuzzy Logic Controller, 2007
  9. Ka-Hou Ao Ieong (Steven), Design of Low-Voltage Analog Baseband with Filter-Sharing for WLAN Transceivers, 2007
  10. Weng-Ieng Mok (Cherry), Characterizing and Solving Analog Impairment of Multi-Stage Analog-to-Digital Converter, 2007
  11. Ma Jun Xia (Meshell), Design of Power Efficient Flash-Interpolation Type ADC for UWB Applications, 2006
  12. Sin Sai Weng (Terry), A Timing-Jitter Noise Analysis for Time-Interleaved Sampled-Data Systems, 2003
  13. Lou Fan, Mismatch-Insensitive N-Path Multirate SC Sigma-Delta Modulator for High-Frequency Applications, 2002
  14. Yin Guohe, Ultra Low-Power SAR ADC for Biomedical Application, (Exchange student from Tsinghua University, Joint-Supervision with Prof. Zhihua Wang, Tsinghua University), On-going
  15. Wang Rui (Ray) , Digital Calibration Techniques for Cyclic Analog-to-Digital Converter, (Exchange student from Tsinghua University, Joint-Supervision with Prof. Zhihua Wang, Tsinghua University), On-going
  16. Chon-In Lao (Louis),Semi-MASH sigma-delta A-to-D Converter for high-speed high-resolution application, On-going
  17. Kin-Kwan Ma (Kobe),High-resolution Analog-to-Digital Converter for Video Application, On-going
  18. Kuai-Fok Au (Robert),Low-power, High Dynamic-Range Sigma-delta A-to-D Converter for Portable Audio System, On-going
  19. Yuan Fei (Frank),High-Resolution Pipeline ADC for video application, On-going
  20. Cheok-Teng_Lei (Tommy),Digital Calibration Technique for High-Resolution Pipeline ADC, On-going
  21. Chon-Hei_Lei (Franco),Digital Distortion Calibration using Dithering in Pipeline ADC, On-going
  22. Jiang Yang (Tim),Low-Power Circuits Techniques for Continuous-Time Sigma-Delta Analog-to-Digital Converter, On-going
  23. Cai Chenyan (Joy), Excess Loop Delay Compensation for Continuous-Time Sigma-Delta Analog-to-Digital Converter, On-going
  24. Zhang Peng, Power-Efficient Pipelined-SAR Analog-to-Digital Converter, (Exchange student from Tsinghua University, Joint-Supervision with Prof. Zhihua Wang, Tsinghua University), On-going
  25. Chen Zhijie, Ultra Low Power Sigma-Delta ADC for Biomedical Readout Front-End, (Exchange student from Tsinghua University, Joint-Supervision with Prof. Zhihua Wang, Tsinghua University), On-going
  26. Wu Wenlan, High-Resolution Low Power Pipelined ADC, On-going
  27. Du Yun, High-speed Continuous-Time Sigma-Delta Modulator, On-going
  28. He Tao,High-bandwidth Low Power Continuous-Time Sigma-Delta Modulator,  On-going

Bachelor Theses (total of 30, 1996 - 2011)


Research Specialty
R&D Project Management Experience

Funded Research Projects

  1. “Research and Development of Comprehensive Data Conversion Platforms in Nanometer CMOS Technology,” funded by Macau Science and Technology Development Fund, 2010 – 2012   
  2. “Research and Development of Comprehensive Data Conversion Platforms in Nanometer CMOS Technology,” funded by Research Committee of University of Macau, 2010 – 2012
  3. “Integrated generalized PWM controller for DC-AC inverter,” funded by Research Committee of University of Macau, 2010 – 2012
  4. “High-Speed, High-Resolution, Low-Power Analog-to-Digital Conversion System with Emerging Scaled CMOS Technology,” funded by Macau Science and Technology Development Fund, 2007 – 2009
  5. “High-Speed, High-Resolution, Low-Power Analog-to-Digital Conversion System with Emerging Scaled CMOS Technology,” funded by Research Committee of University of Macau, 2007– 2009
  6. “Analog Baseband Microelectronics for SoC – Novel CMOS IF Data Conversion Platform For Multi-Standard Wireless Communication” funded from Research Committee of University of Macau, 2003 – 2006
  7. “Integrated Circuit Design of Low-Voltage Low-Power Multirate Analog-Digital System – LVLP/MADIC” funded from Research Committee of University of Macau, 1999 – 2001
  8. “Integrated Circuit Design Of Analog Impulse Sampled Interpolation (ISInt/IC)” funded from Fundação Oriente, 1999 – 2000

Industrial Engineering Projects

  1. “Research & Development of Advanced and Reusable Analog Front-End Semiconductor IP” funded by FDCT, 2006 – 2008
  2. Over 150 engineering projects developed for international IDMs, ASIC Manufactures, Fabless companies in the area of Audio/Voice Codec, Video Analog Front-End, WLAN/GSM Analog Front-End and other Communication or Consumer Electronics products, 2002 – present

Scientific Publications

Patents

  1. Sai-Weng SIN, He-Gong WEI, Franco MALOBERTI, Li DING, Yan ZHU, Chi-Hang CHAN , U-Fat    CHIO, Seng-Pan  U, Rui Paulo da Silva MARTINS” Analog to Digital Converter Circuit”, US Patent , US20120229313 A1, 13, Sep, 2012
  2. He-Gong WEI, U-Fat CHI, Sai-Weng SIN, Seng-Pan  U, Rui Paulo da Silva MARTINS,” Delay generator “US Patent ,US20120286840 A1, 15, Nov, 2012
  3. Yan ZHU, Chi-Hang CHAN , U-Fat CHIO, Sai-Weng SIN, Seng-Pan  U,Rui Paulo da Silva MARTINS, Franco MALOBERTI” bits successive approximation register analog-to-digital converting circuit” US Patent , US20120306679 A1, 6, Dec, 2012
  4. Ka-Hou AO IEONG, Seng-Pan U, “Single-ended to differential-ended converter by open loop based circuitry”, US Patent in application, 2011
  5. Sai-Weng Sin, Li Ding, Yan Zhu, He-Gong Wei, Chi-Hang Chan, U-Fat Chio, Seng-Pan U, R.P.Martins, F.Maloberti, “Two-Step Time-Interleaved SAR-ADC with Reused S&H,” Taiwan Patent in application, 2011.
  6. U-Fat Chio, He-Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “Flash-SAR Two-Step Subranging ADC,” Taiwan Patent in application, 2011.
  7. Sai-Weng Sin, Seng-Pan U and R. P. Martins, “Low-Voltage Finite-Gain Compensation Technique for High-Speed Reset- and Switched-Opamp Circuits,” US Patent in application, 2009.
  8. Sai-Weng Sin, Seng-Pan U and R. P. Martins, “Very Low-Voltage SC-CMFB Technique for Fully-Differential Reset-Opamp Circuits,” US Patent in application, 2009.
  9. Pui-In Mak, Seng-Pan U and R. P. Martins, “Switched Current-Resistor Programmable Gain Array for Low-Voltage Wireless LAN System and Method Using the Same,” US Patent, Pre-Grant Publication No. 2010/0184399, Jul. 2010.
  10. Pui-In Mak, Seng-Pan U and R. P. Martins, “Two-Step Channel Selection for Wireless Transmitter Front-Ends,” US Patent, Granted, No., Jun. 2011.
  11. Pui-In Mak, Seng-Pan U and R. P. Martins, “DC-Offset Canceled Programmable Gain Array for Low-Voltage Wireless LAN System and Method Using the Same,” US Patent, Granted, No. 7,948,309, May. 2011.
  12. Pui-In Mak, Seng-Pan U and R. P. Martins, “Two-Step Channel Selection for Wireless Receiver Front-Ends,” US Patent, Granted, No. 7,529,322, May 2009.
Book
  1. Seng-Pan U, R.P.Martins, J.E.Franca, “Design of Very High-Frequency Multirate Switched-Capacitor Circuits – Extending the Boundaries Of CMOS Analog Front-End Filtering,”, Springer, The Kluwer International Series in Engineering and Computer Science – Analog Circuits and Signal Processing, 2005. (ISBN: 978-0-387-26121-8)
  2. Seng-Pan U, R.P.Martins, J.E.Franca, “Design of Very High-Frequency Multirate Switched-Capacitor Circuits – Extending the Boundaries Of CMOS Analog Front-End Filtering,” China Science Press, The Oversea Electronics & Information Book Excellence Series, 2007 (ISBN: 978-7-03-018249-4).
  3. Sai-Weng Sin, Seng-Pan U, and R.P.Martins, “Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters,” Springer 2010 (ISBN: 978-90-481-9709-5)
  4. Pui-In Mak, Seng-Pan U and R.P. Martins, “Analog-Baseband Architectures and Circuits - for Multistandard and Low-Voltage Wireless Transceivers,” Analog Circuits and Signal Processing, Springer, September 2007. (ISBN: 978-1-4020-6432-6)
Journal Papers
  1. He-Gong Wei, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti, "A 8-bit 400MS/s 2-bit per cycle SAR ADC with Resistive DAC", IEEE Journal of Solid-State Circuits, vol. 47, Issue 11, pp. 2763-2772, Nov 2012. (ISSN : 0018-9200, SCI, EI, IF=3.226)
  2. Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "A 50fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation", IEEE Journal of Solid-State Circuits, vol. 47, Issue 11, pp. 2614 – 2626, Nov 2012. (ISSN : 0018-9200, SCI, EI, IF=3.226)
  3. Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P. Martins and Franco Maloberti, “A 10-bit 100-MS/s Reference-Free SAR ADC in 90nm CMOS,” in IEEE. Journal of Solid-State Circuits, vol. 45, issue 6, pp. 1111-1121, Jun. 2010. (ISSN :  0018-9200, SCI, EI, IF=3.47)
  4. U-Fat Chio, He-Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R. P. Martins and Franco Maloberti, “Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC,” in IEEE Trans. on Circuits and System II – Express Briefs, vol. 57, no. 8, pp. 607 – 611, Aug 2010. (ISSN :  1549-7747, SCI, EI, IF=1.44)
  5. Yan Zhu, U-Fat Chio, He-Gong Wei, Sai-Weng Sin, Seng-Pan U and R.P. Martins, “Linearity Analysis On A Series-Split Capacitor Array for High-Speed SAR ADCs,” in Hindawi VLSI Design, Special Issue "Selected Papers from the Midwest Symposium on Circuits and Systems", vol. 2010, no. 1, pp. 1-8, Apr 2010, Invited. (ISSN :  1548-3746, Print ISBN: 978-1-4244-2166-4, EI)
  6. He-Gong Wei, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “A Rapid Power-Switchable Track-and-Hold Amplifier in 90nm CMOS,” in IEEE Trans. on Circuits and System II – Express Briefs, vol. 57, no. 1, pp. 16-20, Jan 2010. (ISSN :  1549-7747, SCI, EI, IF=1.44)
  7. Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A 1.2-V 10-bit 60-360MS/s Time-Interleaved Pipelined ADC in 0.18um CMOS with Minimized Supply Headroom,” in IET Proceedings - Circuits, Devices and Systems, vol. 4, no. 1, pp. 1-13, Jan 2010. (ISSN :  1751-858X, SCI, EI, IF=0.52)
  8. Sai-Weng Sin, Seng-Pan U, and R.P.Martins, “Generalized Circuit Techniques for Low-Voltage High-Speed Reset- and Switched-Opamps,” in IEEE Transactions on Circuits and Systems I - Regular Papers, vol. 55, no. 8, Sep 2008. (ISSN :  1549-8328, SCI, EI, IF=2.04)
  9. Sai-Weng Sin, U-Fat Chio, Seng-Pan U and R. P. Martins, “Statistical Spectra and Distortion Analysis of Time-Interleaved Sampling Bandwidth Mismatch,” in IEEE Trans. on Circuits and Systems II – Express Briefs, vol. 55, no. 7, pp. 648 – 652, Jul 2008. (ISSN :  1549-7747, SCI, EI, IF=1.44, cited by: 1)
  10. Pui-In Mak, Seng-Pan U and R. P. Martins, "On the Design of Programmable-Gain Amplifier with Built-in Compact DC-Offset Cancellers for Very Low-Voltage WLAN Systems," IEEE Transactions on Circuits and Systems – I: Regular Papers, vol. 55, no. 3, March, 2008. (ISSN :  1549-8328, SCI, EI, IF=2.04, cited by: 2)
  11. Pui-In Mak, Seng-Pan U and R. P. Martins, “An Experimental 1-V Flexible-IF CMOS Analogue-Baseband Chain for IEEE 802.11a/b/g WLAN Receivers,” IET Proceedings - Circuits, Devices and Systems, vol. 1, no. 6, pp. 415-426, Dec. 2007. (ISSN :  1751-858X, SCI, EI, IF=0.52)
  12. Pui-In Mak, Seng-Pan U and R. P. Martins, "Transceiver Architecture Selection - Review, State-of-the-Art Survey and Case Study," IEEE Circuits and Systems Magazine, Vol. 7, Issue 2, pp. 6-25, Jun. 2007. (ISSN :  1531-636X, EI, cited by: 13)
  13. Pui-In Mak, Seng-Pan U and R.P.Martins, “Two-Step Channel Selection – A Novel Technique for Reconfigurable Multistandard Transceiver Front-Ends,” IEEE Transactions on Circuits and Systems-I, Regular Paper, vol.52, pp.1302-1315, Jul., 2005. (ISSN :  1549-8328, SCI, EI, cited by: 6)
  14. Seng-Pan U, Sai-Weng Sin and R.P.Martins, “Exact Spectra Analysis of Sampled Signals with Jitter-Induced Nonuniformly Holding Effects,” IEEE Transactions on Instrumentation and Measurement, vol. 53, pp. 1279-1299, Aug. 2004. (ISSN :  0018-9456, SCI, EI, cited by: 8)
  15. Seng-Pan U, R.P.Martins and J.E.Franca, “A 2.5-V 57-MHz 15-Tap SC Bandpass Interpolating Filter with 320-MHz Output for DDFS System in 0.35-µm CMOS,” IEEE Journal of Solid-State Circuits, vol. 39, No. 1, Jan. 2004. (Print ISBN: 0-7803-7335-9, SCI, EI)
  16. Pui-In Mak, Seng-Pan U and R.P.Martins, “Two-Step Channel Selection Technique by Programmable Digital-Double Quadrature Sampling for Complex Low-IF Receivers,” IEE Electronics Letters, vol. 39, no. 11, pp. 825-827, May 2003. (ISSN :  0013-5194, SCI, EI, cited by: 1)
  17. Seng-Pan U, R.P. Martins and J.E.Franca, “Improved Switched-Capacitor Interpolators with Reduced Sample-and-Hold Effects,” IEEE Transactions on Circuits and Systems – II: Analog and Digital Signal Processing, vol.47, No.8, pp.665-684, Aug. 2000. (ISSN :  1057-7130, SCI, EI, cited by: 7)
  18. Seng-Pan U, R.P.Martins and J.E.Franca, “Offset-& Gain-Compensated and Mismatch-Free SC Delay Circuit with Flexible Implementation”, IEE Electronics Letters, vol. 35, No.3, pp.188-189, Feb. 4th. 1999. (ISSN :  0013-5194, SCI, EI)
  19. Seng-Pan U, R.P.Martins and J.E.Franca, “Impulse Sampled FIR Interpolation with SC Active-Delayed Block Polyphase Structures”, IEE Electronics Letters, vol. 34, No.5, pp.443-444, Mar. 5th. 1998. (ISSN :  0013-5194, SCI, EI, cited by: 3)
  20. Seng-Pan U, R.P.Martins and J.E.Franca, “Switched-Capacitor Interpolators Without the Input Sample-and-Hold Filtering Effect”, IEE Electronics Letters, vol. 32, No.10, pp.879-881, May 9th. 1996. (ISSN :  0013-5194, SCI, EI, cited by: 4)
Conference Papers

IEEE International Solid-State Circuits Conference ISSCC
  1. He-Gong Wei, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R. P. Martins and F. Maloberti, “A 0.024mm2 8-bit 400 MS/s SAR ADC with 2-bit per Cycle and Resistive DAC in 65 nm CMOS,” in IEEE International Solid-State Circuit Conference (ISSCC),  vol. 54, pp.188-189, Feb 2011. (ISSCC Silk Road Award)
  2. Seng-Pan U, R.P.Martins, J.E.Franca, “A 2.5 V, 57 MHz, 15-Tap SC Bandpass Interpolating Filter with 320 MHz Output Sampling Rate in 0.35mm CMOS,” IEEE International Solid State Circuits Conference (ISSCC) Digest of Technical Papers, pp.380-381/475, San Francisco, Feb. 2002.
IEEE Asian Solid-State Circuits Conference A-SSCC
  1. Jianyu Zhong, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R. P. Martins, "Inter-Stage Gain Error Self-Calibration of a 31.5fJ 10b 470MS/s Pipelined-SAR ADC", IEEE Asian Solid-State Circuit Conference – (A-SSCC), Nov 2012.
  2. Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U , R.P.Martins­ , Franco Maloberti, “A 35 fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation,” Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 61-64, Nov.2011.
  3. Si-Seng Wong,U-Fat Chio, He-Gong Wei, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin, Seng-Pan U, R. P. Martins, "A 4.8-bit ENOB 5-bit 500MS/s Binary-Search ADC with Minimized Number of Comparators,” Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 73-76, Nov.2011.
  4. Chi-Hang Chan, Yan Zhu, U-Fat Chio, Sai-Weng Sin, Seng-Pan U , R.P.Martins, " A Reconfigurable Low-Noise Dynamic Comparator with Offset Calibration in 90nm CMOS,” Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 233-236, Nov.2011.
  5. He-Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A Process-insensitive Current-Controlled Delay Generator with Threshold Voltage Compensation,” in IEEE Asian Solid-State Circuit Conference (A-SSCC), paper no. 8-4 , Nov, 2010.
  6. Sai-Weng Sin, He-Gong Wei, U-Fat Chio, Yan Zhu, Seng-Pan U, R.P. Martins and Franco Maloberti, " On-Chip Small Capacitor Mismatches Measurement Technique using Beta-Multiplier-Biased Ring Oscillator,” in Proc. of 2009 IEEE Asian Solid-State Circuit Conference (A-SSCC), pp. 49-52, Nov 2009.
IEEE European Solid-State Circuits Conference ESSCIRC
  1. Guohe Yin, He-Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Zhihua Wang, R.P. Martins, "A 0.024mm2 4.9 fJ 10-Bit 2MS/s SAR ADC in 65 nm CMOS", IEEE European Solid-State Circuits Conference – ESSCIRC 2012, pp. 377-380, Sept 2012.
  2. Rui Wang, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, "A 12-Bit 110MS/S 4-Stage Single-Opamp Pipelined SAR ADC with Ratio-Based GEC Technique", IEEE European Solid-State Circuits Conference – ESSCIRC 2012, pp. 265-268, Sept 2012.
  3. U-Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, "A 7-bit 300-MS/s Subranging ADC with Embedded Threshold & Gain-Loss Calibration", in Proc. IEEE European Solid-State Circuits Conference – ESSCIRC 2011, pp. 363-366, Finland, September 2011.
  4. Sai-Weng Sin, Li Ding, Yan Zhu, He-Gong Wei, Chi-Hang Chan, U-Fat Chio, Seng-Pan U, R.P.Martins and F. Maloberti, "An 11b 60MS/S 2.1mW Two-Step Time-Interleaved SAR-ADC with Reused S&H", in Proc. IEEE European Solid-State Circuits Conference – ESSCIRC 2010, Seville, Spain, September 2010.
  5. J.Risques, Seng-Pan U, Kuok Vai Chiang, Ka Fai Chang, Keng Chong Lai, Jorge Duarte, Vasco Amaro, “A Very Area/Power Efficient Mixed Signal Circuit For Voice Signal Processing In Pure 0.18 Digital Technology,” in Proc. IEEE European Solid State Circuits Conference 2003 – ESSCIRC'03 Portugal, Sep. 2003.
IEEE Symposium on VLSI Circuits VLSI
  1. Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, R. P. Martins, "A 34fJ 10b 500 MS/s Partial-Interleaving Pipelined SAR ADC", 2012 Symposium on VLSI Circuits Digest of Technical Papers, page 90-91;13-15 June 2012, pp. 90-91, Jun 2012.
  2. Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R. P. Martins, "A 3.8mW 8b 1GS/s 2b/cycle Interleaving SAR ADC with Compact DAC Structure", 2012 Symposium on VLSI Circuits Digest of Technical Papers, page 86-87;13-15 June 2012, pp. 86-87, Jun 2012.
  3. Pui-In Mak, Seng-Pan U and R. P. Martins, “A 1V 14mW-per-Channel Flexible-IF CMOS Analog-Baseband IC for 802.11a/b/g Receivers,” IEEE Symposium on VLSI Circuits, Digest Technical papers (VLSI), pp.288-289, Jun. 2006.
IEEE Custom Integrated Circuits Conference CICC
  1. Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R. P. Martins, A 2.3mW 10-bit 170MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC IEEE Custom Integrated Circuits Conference CICC 2012, Sept 2012.
  2. Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R. P. Martins, "A 2.3mW 10-bit 170MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC", IEEE Custom Integrated Circuits Conference – CICC 2012, Sept 2012.
  3. Pui-In Mak, Seng-Pan U, R. P. Martins, “A 1-V Transient-Free and DC-Offset-Canceled PGA with a 17.1-MHz Constant Bandwidth over 52-dB Control Range in 0.35-µm CMOS,” in Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pp. 649-652, USA, Sep. 2005.
IEEE International Symposium on Circuits and Systems ISCAS
  1. Tao He, Yang Jiang, Yun Du, Sai-Weng Sin, Seng-Pan U and Rui.P. Martins, “A 10MHz BW 78dB DR CT ΣΔ Modulator with Novel Switched High Linearity VCO-Based Quantizer”, in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 65-69, Korea, May 2012.
  2. Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, “A Voltage Feedback Charge Compensation Technique for Split DAC Architecture in SAR ADCs”, in Proc. of 2010 IEEE International Symposium on Circuits and Systems (ISCAS),pp. 607-611, May. 2010.
  3. He-Gong Wei, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U and R.P. Martins, “A Power Scalable 6-bit 1.2GS/s Flash ADC with Power on/off Track-and-Hold and Preamplifier”, in Proc. of 2008 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 5-8, Seattle, USA, May 2008.
  4. Weng-Ieng Mok, Pui-In Mak, Seng-Pan U, R.P.Martins, “A Highly-Linear Successive-Approximation Front-End Digitizer with Built-in Sample-and-Hold Function for Pipeline/Two-Step ADC,” to be appeared in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), USA, May 2007.
  5. Pui-In Mak, Seng-Pan U and R. P. Martins, “Design and Test Strategy underlying a Low-Voltage Analog-Baseband IC for 802.11a/b/g WLAN SiP Receivers,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp.2473-2476, Island of Kos, Greece, May 2006.
  6. Sai-Weng Sin, Seng-Pan U and R. P. Martins, “A Novel Low-Voltage Finite-Gain Compensation Technique for High-Speed Reset- and Switched-Opamp Circuits,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp.3794-3797, Greece, May 2006.
  7. Jun-Xia Ma, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “A Power-Efficient 1.056 GS/s Resolution-Switchable 5-Bit/6-Bit Flash ADC for UWB Applications,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp.4305-4308, Greece, May 2006.
  8. Chon-In Lao, Seng-Pan U and R. P. Martins, “A Highly-Efficient Semi-Mash Structure for Bandpass Sigma-Delta Modulator with Double-Sampling Mismatch-Free Resonator,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS),  pp.581-584, Greece, May 2006.
  9. Kin-Sang Chio, Seng-Pan U and R. P. Martins, “A Dual-Mode Low-Distortion Sigma-Delta Modulator with Relaxing Comparator Accuracy,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp.1892-1895, Greece, May 2006.
  10. Sai-Weng Sin, Seng-Pan U and R.P.Martins, "A Novel Low-Voltage Cross-Coupled Passive Sampling Branch for Reset- and Switched-Opamp Circuits," in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), vol.2, pp.1585-1588, Kobe, Japan, May 2005.
  11. Sai-Weng Sin, Seng-Pan U and R.P.Martins, "A Novel Very Low-Voltage SC-CMFB Technique for Fully-Differential Reset-Opamp Circuits," in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), vol.2, pp.1581-1584, Kobe, Japan, May 2005.
  12. Ka-Hou Ao Ieong, Chong-Yin Fok, Pui-In Mak, Seng-Pan U and R.P.Martins, “A Frequency Up-Conversion and Two-Step Channel Selection Embedded CMOS D/A Interface,” in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp.392-395, Kobe, Japan, May 2005.
  13. Chon-In Lao, Seng-Pan U and R.P.Martins, "High-order Cascade Sigma-Delta Modulator using Semi-MASH Sub-stage," in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp.3095-3098,Kobe, Japan, May 2005.
  14. Kin-Sang Chio, Seng-Pan U and R.P.Martins, "A Robust 3rd Order Low-Distortion Multi-bit Sigma-Delta Modulator with Reduced Number of Op-amp Technique for WCDMA," in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp.3099-3102, Kobe, Japan, May 2005.
  15. Sai-Weng Sin, Seng-Pan U and R.P.Martins, “A generalized timing-skew-free, multi-phase clock generation platform for parallel sampled-data systems,” in Proc. of 2004 IEEE International Symposium on Circuits and Systems (ISCAS), vol.1, pp. I-369 – I-372 , May 2004.
  16. Pui-In Mak, Seng-Pan U, R.P.Martins, “A Low-IF/Zero-IF Reconfigurable Receiver with Two-Step Channel Selection Technique for Multistandard Applications,” in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp.417-420, Vancouver, Canada, May 2004.
  17. Pui-In Mak, Kin-Kwan Ma, Weng-Ieng Mok, Chi-Sam Sou, Kit-Man Ho, Cheng-Man Ng, Seng-Pan U, R.P.Martins, “An I/Q-Multiplexed and Op-Amp-Shared CMOS Pipelined ADC with an A-DQS S/H Front-End for Two-Step-Channel-Select Low-IF Receiver,” in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp.1068-1071, Vancouver, Canada, May 2004.
  18. Sai-Weng Sin, Seng-Pan U, R.P.Martins, "Timing-Mismatch Analysis in High-Speed Analog Front-End with Nonuniformly Holding Output,” in Proc. of IEEE International Symposium on Circuits and Systems 2003 - "ISCAS'2003, Bangkok, Thailand, May 2003.
  19. Chon-In Lao, Ho-Ieng Ieong, Kuai-Fok Au, Kuok-Hang Mok, Seng-Pan U, R.P.Martins, "A 10.7-MHz Bandpass Sigma-Delta Modulator using Double-Delay Single-Opamp SC Resonator with Double-Sampling," in Proc. of IEEE International Symposium on Circuits and Systems 2003 - "ISCAS'2003, Bangkok, Thailand, May 2003.
  20. Seng-Pan U, R.P.Martins,  J.E.Franca, "Design and Analysis of Low Timing-Skew Clock Generation for Time-Interleaved Sampled-Data Systems," in Proc. of IEEE International Symposium on Circuits and Systems 2002 - "ISCAS'2002, Volume IV, pp. 441-444, Scottsdale, Arizona, U.S.A., May 2002.
  21. Seng-Pan U, R.P.Martins, J.E.Franca, “A High-Speed Frequency Up-Translated SC Bandpass Filter With Auto-Zeroing For DDFS Systems,” in Proc. of The 2001 IEEE International Symposium on Circuits and Systems (ISCAS’2001), Volume. I, pp.320-323, Sydney, Australia, May 2001.
  22. Seng-Pan U, R.P.Martins, J.E.Franca, “High-Frequency Low-Power Multirate SC Realizations For NTSC/PAL Digital Video Filtering,” in Proc. of The 2001 IEEE International Symposium on Circuits and Systems (ISCAS’2001), Volume. I, pp.204-207, Sydney, Australia, May, 2001.
  23. Seng-Pan U, R.P.Martins, J.E.Franca, “A Linear-Phase Halfband SC Video Interpolation Filter With Coefficient-Sharing And Gain- & Offset-Compensation,” in Proc. of The 2000 IEEE International Symposium on Circuits and Systems (ISCAS’2000), Volume. III, pp.177-180, Geneva, Switzerland, May 28-31, 2000.
  24. Seng-Pan U, R.P.Martins, J.E.Franca, “Highly Accurate Mismatch-Free SC Delay Circuits With Reduced Finite Gain And Offset Sensitivity,” in Proc. of 1999 IEEE International Symposium on Circuits and Systems (ISCAS’99), Volume.2, pp.57-60, USA, May 1999.
  25. Seng-Pan U, R.P.Martins, J.E.Franca, “High Performance Multirate SC Circuits With Predictive Correlated Double Sampling Technique,” in Proc. of 1999 IEEE International Symposium on Circuits and Systems (ISCAS’99), Volume.2, pp.77-80, USA, May 1999.
  26. Seng-Pan U, R.P.Martins, J.E.Franca, “Intermittent Polyphase SC Structures for FIR Rational Interpolation,” in Proc. of IEEE International Symposium on Circuits and Systems 1997 - "ISCAS'1997, Volume.I, pp.121-124, Hong Kong, Jun 1997.
IEEE International Conference on Electronics, Circuits and Systems ICECS
  1. Yang Jiang, Kim-Fai Wong, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “A Fixed-Pulse Shape Feedback Technique with reduced clock-jitter sensitivity in Continuous-Time sigma-delta modulators” in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 547-550, Dec, 2010.
  2. Yang Jiang, Kim-Fai Wong, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “A Fixed-Pulse Shape Feedback Technique with reduced clock-jitter sensitivity in Continuous-Time sigma-delta modulators” in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 547-550, Dec, 2010.
  3. Yan Zhu, U-Fat Chio, He-Gong Wei, Sai-Weng Sin, Seng-Pan U and R.P. Martins, "A Power-Efficient Capacitor Structure for High-Speed Charge Recycling SAR ADCs,” in Proc. of 2008 IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 642-645, Aug 2008.
  4. Pui-In Mak, Seng-Pan U, R.P. Martins, “A Front-to-Back-end Modeling of I/Q Mismatch Effects in a Complex-IF receiver for large image-rejection,” in Proc. of IEEE International Conference of Electronics, Circuits and Systems (ICECS’ 2003), pp. 631-634, Sharjah, United Arab Emirates, 2003.
  5. Pui-In Mak, Chi-Sam Sou, Seng-Pan U, R.P. Martins, “Frequency-Downconversion and Channel Selection Sample-and-Hold circuit with A-DQS technique for Complex Low-IF Wireless Receivers,” in Proc. of IEEE International Conference of Electronics, Circuits and Systems (ICECS’2003), pp. 479-482, Sharjah, United Arab Emirates, 2003.
  6. Fan Lou, Seng-Pan U, R.P.Martins, “N-Path Multirate Sigma-Delta Modulator For High Frequency Application,” in Proc. of The IEEE International Conference on Electronics, Circuits and Systems (ICECS’2002) pp.315-318, Sep. 2002.
  7. Seng-Pan U, R.P.Martins, J.E.Franca, “A Novel Half-Band SC Architecture for Effective Analog Impulse Sampled Interpolation,” in Proc. of The 5th IEEE International Conference on Electronics, Circuits and Systems-ICECS’98, pp.389-403, Lisbon, Portugal, Sep. 1998.
  8. Seng-Pan U, R.P.Martins, J.E.Franca, “New Impulse Sampled IIR Switched-Capacitor Interpolators,” in Proc. of The Third IEEE International Conference on Electronics, Circuits and Systems (ICECS’96), pp.203-206, Rodos, Greece, Oct. 1996.
IEEE Midwest Symposium on Circuits and Systems MWSCAS
  1. Chen-Yan Cai, Yang Jiang, Sai-Weng Sin, Seng-Pan U R.P. Martins, "An ELD Tracking Compensation Technique for Active-RC CT ΣΔ Modulators", IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS), 2012, Aug 2012
  2. Yang Jiang, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U and Rui P. Martins, “Clock-Jitter Sensitivity Reduction in CT ΣΔ Modulators Using Voltage-Crossing Detection DAC,” to appear soon in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2011, Korea, August 2011.
  3. Chen-Yan Cai, Yang Jiang, Sai-Weng Sin, Seng-Pan U and Rui. P. Martins, “A Passive Excess-Loop-Delay Compensation Technique for Gm-C Based Continuous-Time ΣΔ Modulators,” to appear soon in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2011, Korea, August 2011.
  4. Tao He, Yun Du, Yang Jiang, Sai-Weng Sin, Seng-Pan U and Rui P. Martins, “A Dual-VCO-Based Quantizer with Highly Improved Linearity and Enlarged Dynamic Range,” to appear soon in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2011, Korea, August 2011.
  5. Peng Zhang, Zhijie Chen, He-Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Zhihua Wang, “A Charge Pump Based Timing-Skew Calibration for Time-Interleaved ADC,” to appear soon in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2011, Korea, August 2011.
  6. Zhijie Chen, Peng Zhang, Hegong Wei, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Zhihua Wang, “Noise Shaping Implementation in Two-Step/SAR ADC Architectures Based on Delayed Quantization Error,” to appear soon in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2011, Korea, August 2011.
  7. Jianyu Zhong, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, “A Multi-Merged-Switched Redundant Capcitive DACs for 2b/cycle SAR ADC,” to appear soon in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2011, Korea, August 2011.
  8. Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A Threshold-Embedded Offset Calibration Technique for Inverter-Based Flash ADCs,” in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010, pp. 489-492, August 2010.
  9. Kim-Fai Wong, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “Level-Shifting Variable Current Charging Technique for High-Speed Comparator-Based Switched-Capacitor Circuits,” to appear soon in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010, , pp. 566-569, August 2010.
  10. Si-Seng Wong, U-Fat Chio, Hou-Lon Choi, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A Power Effective 5-bit 600 MS/s Binary-Search ADC with Simplified Switching,” to appear soon in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010, pp. 29-32 August 2010.
  11. Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “Parasitics Nonlinearity Cancellation Technique for Split DAC Architecture by Using Capacitive Charge-Pump,” to appear soon in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010, pp. 889-892 August 2010.
  12. Kim-Fai Wong, Sai-Weng Sin, Seng-Pan U and R.P. Martins, " A Modified Charging Algorithm for Comparator-Based Switched-Capacitor Circuits,” in Proc. of 2009 Midwest Symposium on Circuits and Systems (MWSCAS), pp. 86-89, Aug. 2009.
  13. Yan Zhu, U-Fat Chio, He-Gong Wei, Sai-Weng Sin, Seng-Pan U and R.P. Martins, " Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs,” in Proc. of 2008 Midwest Symposium on Circuits and Systems (MWSCAS), pp. 922-925, Aug 2008 .
  14. Weng-Ieng Mok, Pui-In Mak, Seng-Pan U, R.P.Martins, “Modeling of Noise Sources in Reference bVoltage Generator for Very-High-Speed Pipelined ADC,” in Proc. of the 47th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), vol.1 , pp. 5-8, Hiroshima, Japan, July 2004.
    (2nd Prize, MWSCAS Student Paper Contest)
  15. Fan Lou, Seng-Pan U, R.P.Martins, "Mismatch-insensitive N-Path Multirate Sigma-Delta Modulator for High-Frequency Applications," in Proc. of The 45th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS’2002), Aug. 2002.
  16. Seng-Pan U, R.P.Martins, J.E.Franca, “Impulse Sampled Intermittent SC FIR Rational Decimators With Double-Sampling,” in Proc. of 1997 IEEE 40th Midwest Symposium on Circuits and Systems, pp.977-980, Sacramento, USA, Aug. 1997.
  17. Seng-Pan U, R.P.Martins, J.E.Franca, “Switched-Capacitor Finite Impulse Response Interpolators Without the Input Sample-and-Hold Filtering Effect,” inProc. of 1996 IEEE 39th Midwest Symposium on Circuits and Systems, Ames, Iowa, USA, Aug. 1996.
IEEE Asia-Pacific Conference on Circuits and Systems APCCAS
  1. Zhijie Chen, Yang Jiang, Chenyan Cai, He-Gong Wei, Sai-Wen Sin, Seng-Peng U, Zhihua Wang, R. P. Martins, "A 22.4µW 80dB SNDR ΣΔ Modulator with Passive Analog Adder and SAR Quantizer for EMG Application” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2012.
  2. Yun Du, Tao He, Yang Jiang, Sai-Weng Sin, Seng-Pan U, R. P. Martins, "A Robust NTF Zero Optimization Technique for Both Low and High OSRs Sigma-Delta Modulators", IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2012.
  3. Tao He, Yun Du, Yang Jiang, Sai-Weng Sin, Seng-Pan U, R. P. Martins, "A DT 0-2 MASH Modulator with VCO-Based Quantizer for Enhanced Linearity", IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2012.
  4. Wen-Lan Wu, Sai-Weng Sin, Seng-Pan U, R. P. Martins, "A 10-bit SAR ADC With Two Redundant Decisions and Splitted-MSB-Cap DAC Array", IEEE ASIA Pacific Conference on Circuits and system (APCCAS), 2012.
  5. Yang Jiang, Kim-Fai Wong, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “A Reduced Jitter-Sensitivity Clock Generation Technique for Continuous-Time ΣΔ Modulators,” in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 1011-1014, Dec. 2010.
  6. Li Ding, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “An Efficient DAC and Interstage Gain Error Calibration Technique For Multi-Bit Pipelined ADCs” in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 208-211, Dec. 2010.
  7. He-Gong Wei, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U and R.P. Martins, " A Process- and Temperature- insensitive Current-Controlled Delay Generator for Sampled-Data Systems,” in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 1192-1195, Dec. 2008.
  8. U-Fat Chio, He-Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U and R.P. Martins, " A Self-Timing Switch-Driving Register by Precharge-Evaluate Logic for High-Speed SAR ADCs” in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 1164-1167, Dec. 2008.
  9. Li Ding, Sio Chan, Kim-Fai Wong, Sai-Weng Sin, Seng-Pan U and R.P. Martins, " A Pseudo-Differential Comparator-Based Pipelined ADC with Common Mode Feed Forward Technique” in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 276-279, Dec. 2008.
  10. Ka-Hou Ao Ieong, Seng-Pan U and R. P. Martins, “A 1-V 2.5-mW Transient-Improved Current-Steering DAC using Charge-Removal-Replacement Technique,” to be appeared in The Proceeding of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Dec. 2006.
IEEE Instrumentation and Measurement Technology Conference IMTC
  1. Seng-Pan U, Sai-Weng Sin, R.P.Martins, "Spectra Analysis of Nonuniformly Holding Signals for Time-Interleaved Systems with Timing Mismatches," in IEEE Instrumentation and Measurement Technology Conference - IMTC'2003, Vail, Colorado, U.S.A., pp. 1298-1301, May 2003.
IEEE International Conference on Acoustics, Speech & Signal Processing ICASSP
  1. Sai-Weng Sin, Seng-Pan U, R.P.Martins, "Quantitative Noise Analysis of Jitter-Induced Non-Uniformly Sampled-And-Held Signals," in IEEE International Conference on Acoustics, Speech and Signal Processing – “ICASSP'2003", Hong Kong, China, pp.VI-253-256, April 2003.
IEEE International Conference on ASIC ASICON
  1. Pui-In Mak, Seng-Pan U, R.P. Martins, “A Programmable Switched-Capacitor A-DQS Frequency Downconverter for Two-Step Channel Selection Wireless Receiver,” in Proc. of IEEE International Conference on ASIC - ASICON’2003, pp.573-576, Beijing, China, Oct. 2003.
    (Outstanding Student Paper Award)
  2. Chon-In Lao, Seng-Pan U, R.P.Martins,  “Bandpass Sigma-Delta Modulator SIMULINK® Non-Idealities Model with Behavior Simulation,” in Proc. of IEEE International Conference on ASIC - ASICON’2003, pp.685-688, Beijing, China, Oct. 2003.
  3. Seng-Pan U, Ho-Ming Cheong, Iu-Leong Chan, Keng-Meng Chan, U-Chun Chan, Mantou Liu, R.P.Martins, J.E.Franca, “An SC CCIR-601 Video Restitution Filter With 13.5 Msample/S Input and 108 Msample/S Output,” in Proc. of IEEE International Conference on ASIC - ASICON’2001, pp.374-377, Shanghai, China, Oct. 2001.
IEEE International Symposium on Radio-Frequency Integration Technology RFIT
  1. Seng-Pan U, Sai-Weng Sin, Yan Zhu, U-Fat Chio, He-Gong Wei and, R. P. Martins, “Design Techniques for Nanometer Wideband Power-Efficient CMOS ADCs,” in Proc. of IEEE International Symposium on Radio-Frequency Integration Technology – RFIT’2011, pp. 173-176, Beijing, China, Nov. 2011.
IEEJ International Analog VLSI Workshop - AVLSIWS
  1. Pui-In Mak, Seng-Pan U, R.P.Martins, “A Power-and-Area Efficient, Multifunctional CMOS A/D Interface for a Low-IF/Zero-IF Reconfigurable Receiver,” in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS), pp. 233-238, Macao, China, Oct. 2004.
    (Best Paper Award)
  2. Pui-In Mak, Ka-Hou Ao Ieong, Chong-Yin Fok, Seng-Pan U, R.P.Martins, “A Complex Low-IF Transceiver Architecture for Relaxing Phase Noise and Settling Time Requirements of RF PLL-FS,” in Proc. of IEEJ (7th) International Analog VLSI Workshop, pp. 221-226, Macao, China, Oct. 2004.
  3. Hon-Weng Chong, Kai-Yiu Che, Seng-Pan U, R.P.Martins, “A 1-V 2.56-MHz Clock-Rate CMOS Multi-bit Sigma-Delta Modulator with Reset-Opamp Technique and Pseudo Data-Wwighted-Averaging for Portable Audio Data Acquistion,” in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS), pp. 180-185, Macau SAR, China, October 2004.
  4. Weng-Ieng Mok, Pui-In Mak, Seng-Pan U, R.P.Martins, “Model, Characterization and Solutions of Unstable Reference Voltage for Very-High-Speed Pipelined A/D Converters,” in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS), pp. 138-143, Macau SAR, China, October 2004.
  5. Kai-Yiu Che, Hon-Weng Chong, Seng-Pan U, R.P.Martins, “A 1-V 5.12-MHz Sampling-Rate 13-bit CMOS Sigma-Delta Modulator Using Reset-Opamp Technique for Portable Aduio Data Acquistion System,” in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS), pp. 186-191, Macau SAR, China, October 2004.
  6. Ka-Hou Ao Ieong, Chong-Yin Fok, Seng-Pan U, R.P.Martins, “A Multistandard Transmitter D/A Interface with Embedded Frequency Up-Conversion and Two-Step Channel Selection,” in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS), pp. 215-220, Macau, China, Oct. 2004.
China Association Science and Technology Conference of Young Scientists CAST
  1. Seng-Pan U, “A Novel Frequency-Translated Filtering Technique for DDFS Systems and its Integrated Circuit Implementation,” Proc. of The 4th China Association Science and Technology (CAST) Conference of Young Scientists, pp.46-47, Beijing, China, Oct. 2001 (in Chinese).
  2. Seng-Pan U, “A Novel Impulse Sampled Interpolation Technique for Efficient and Accurate Analog Multirate Signal Processing,” in Proc. of The 3rd China Association for Science and Technology (CAST) Conference of Young Scientists, Beijing, China, Aug. 1998 (in Chinese).
Other International Conference
  1. Arshad Hussain, Sai-Weng Sin, Seng-Pan U, Rui P. Martins, "Hybrid Loopfilter Sigma-Delta Modulator With NTF Zero Compensation", International SoC Design Conference – ISOCC, pp. 76-79, Nov 2011
  2. Arshad Hussain, Sai-Weng Sin, Seng-Pan U, Rui P. Martins, "NTF Zero Compensation Technique For Passive Sigma-Delta Modulator", IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), pp. 82-851, Oct 2011
  3. Yuan Fei, Sai-Weng Sin, Seng-Pan U, R. P. Martins, "A Nonlinearity Digital Background Calibration Algorithm for 2.5bit/stage Pipelined ADCs With Opamp Sharing Architecture", IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), pp. 1-4, Oct 2011.
  4. Rui Wang, U-Fat Chio, Chi-Hang Chan, Li Ding, Sai-Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, "A time-efficient dither-injection scheme for pipelined SAR ADC", IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), pp. 9-12, Oct 2011
  5. Bo Sun, U-Fat Chio, Chi-Seng Lam, Ning-Yi Dai, Man-Chung Wong, Chi-Kong Wong, Sai-Weng Sin, Seng-Pan U, R. P. Martins, "A FPGA-Based Power Electronics Controller for Hybrid Active Power Filters", IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), pp. 25-28, Oct 2011
  6. Bo Sun, Ning-Yi Dai, U-Fat Chio, Man-Chung Wong, Chi-Kong Wong, Sai-Weng Sin, Seng-Pan U, R. P. Martins, "FPGA-based Decoupled Double Synchronous Reference Frame PLL for Active Power Filters", 2011 6th IEEE Conference on Industrial Electronics and Applications (ICIEA), pp. 2145 – 2150, 2011
  7. Yuan Fei, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “A Digital Background Nonlinearity Calibration Algorithm for Pipelined ADCs,” IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), 2010.
  8. Si-Seng Wong, Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “Parasitic Calibration by Two-Step Ratio Approaching Techinque for Split Capacitor Array SAR ADCs,” in Proc. of 2009 International SoC Design Conference (ISOCC), invited, pp. 333-336, Nov. 2009.
  9. Chi-Hang Chan, Yan Zhu, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A Voltage-Controlled Capacitance Offset Calibration Technique for High Resolution Dynamic Comparator,” in Proc. of 2009 International SoC Design Conference (ISOCC), invited, pp. 392-395, Nov. 2009.
  10. Cheok-Teng Lei, Seng-Pan U and R. P. Martins, “High-Speed Robust Level Converter for Ultra-Low Power 0.6-V LSIs to 3.3-V I/O,” in Proc. of 2009 International SoC Design Conference (ISOCC), invited, pp. 396-399, Nov. 2009.
  11. U-Fat Chio, Hou-Lon Choi, Chi-Hang Chan, Si-Seng Wong, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “Comparator-Based Successive Folding ADC,” IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), pp. 117-120, Nov. 2009.
    (Bronze Leaf Certificate)
  12. Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, “Novel Timing-Skew-Insensitive, Multi-Phase Clock Generation Scheme For Parallel Dac And N-Path Filter,” Proceedings of the 4th Regional Inter-University Postgraduate Electrical and Electronics Engineering Conference (RIUPEEEC), paper 32, Macau, Jul. 2006.
  13. Ka-Hou Ao Ieong, Seng-Pan U, Rui Paulo Martins, “Design of a 1-V 10-bit 120-MS/s Current-Steering DAC with Transient-Improved Technique,” Proceedings of the 4th Regional Inter-University Postgraduate Electrical and Electronics Engineering Conference (RIUPEEEC), paper 33, Macau, Jul. 2006.
  14. Weng-Ieng Mok, Pui-In Mak, Seng-Pan U, R. P. Martins, “A Novel Architecture of Comparator-Mismatch-Free Multi-Bit Pipeline ADC,” Proceedings of the 4th Regional Inter-University Postgraduate Electrical and Electronics Engineering Conference (RIUPEEEC), paper 31, Macau, Jul. 2006.
  15. Chon-In Lao, Seng-Pan U, R. P. Martins, “A Expandable and Extendable High-order Semi-MASH Sigma-Delta Modulator,” Proceedings of the 4th Regional Inter-University Postgraduate Electrical and Electronics Engineering Conference (RIUPEEEC), paper 15, Macau, Jul. 2006.
  16. Jun-Xia Ma, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “1.8-V 1.056-Gs/S 6-B Flash-Interpolation ADC For Mb-Ofdm Uwb Applications,” Proceedings of the 4th Regional Inter-University Postgraduate Electrical and Electronics Engineering Conference (RIUPEEEC), paper 25, Macau, Jul. 2006.
  17. Ngai Kong, Seng-Pan U, R. P. Martins, “A Novel Current-Mode Reconfigurable Memebership Function Circuti For Mixed-Signal Fuzzy Hardware,” Proceedings of the 4th Regional Inter-University Postgraduate Electrical and Electronics Engineering Conference (RIUPEEEC), paper 24, Macau, Jul. 2006.
  18. Pui-In Mak, Seng-Pan U, R. P. Martins, “Multistandard-Compliant Receiver Architecture with low-voltage Implementation,” in Proceedings of Ph.D. Research In Micro-Electronics & Electronics (PRIME), pp. 223-226, Lausanne, Switzerland, Jul. 2005. (Silver Leaf Certificate)
  19. Sai-Weng Sin, Seng-Pan U, R. P. Martins, “Novel low-voltage circuit techniques for fully-differential reset- and switched-opamps,” in Proceedings of Ph.D. Research In Micro-Electronics & Electronics (PRIME), Switzerland, pp. 398-401, Lausanne, Switzerland, Jul. 2005.
  20. Weng-Ieng Mok, Pui-In Mak, Seng-Pan U, R. P. Martins, “On-Chip Unsteady Reference Voltage Compensation Techniques for Very-High-Speed Pipelined ADC,” in Proceedings of Regional Inter-University Postgraduate Electrical and Electronic Engineering Conference (RIUPEEEC), pp. 276-280, Hong Kong, China, Jun. 2005.
  21. Kin-Sang Chio, Seng-Pan U, R.P.Martins, “A novel low-voltage 2nd-order sigma-delta modulator with double-sampling for GSM/DECT/WCDMA,” in Proc. of International Conference on Communications, Circuits and Systems (ICCCAS), pp. 1146-1150, vol. 2, Jun. 2004.
  22. Pui-In Mak, Weng-Ieng Mok, Seng-Pan U, R.P. Martins, “I/Q Imbalance Modeling of Quadrature Transceiver Analog Front-Ends in SIMULINK,” in Proc. of the 58th IEEE International Conference on Vehicular Technology, pp. 2371-2374, Orlando, Florida, USA. Oct. 2003.
  23. Pui-In Mak, Seng-Pan U, R.P. Martins, “A Novel IF channel Selection Technique by Analog- Double quadrature Sampling for Complex low-IF receivers,” in Proc. of IEEE International Conference of Communication Technology, pp.1238-1241, Beijing, China, Apr.2003.
  24. Seng-Pan U, R.P.Martins, J.E.Franca, “Experimental Results of SC Fractional Multirate Converters with Intermittent Polyphase Structures,” in Proc. Of The First Portugal-China Workshop on Solid-State Circuits, pp.28-29, Shanghai, China. Oct. 25-27, 2000.
  25. Seng-Pan U, R.P.Martins, J.E.Franca, “A 120 MHz SC 4th-Order Elliptic Interpolation Filter with Accurate Gain and Offset Compensation For Direct Digital Frequency Synthesizer,” in Proc. of The First IEEE Asia-Pacific Conference on ASICs (AP-ASIC’99), pp.1-4, Korea, Aug. 1999.
  26. Guohe Yin, He-Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Zhihua Wang, Rui Paulo Martins, " A 0.014mm2 4.8fJ/step 10-bit 1-MS/s SAR ADC for Bio-medical Applications,” to be submitted.
Macau Local Journals
  1. Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A 1-V 10b 40MS/s Pipelined ADC with Low-Voltage Circuit Techniques in 0.18um CMOS”, 澳門機電工程專業協會(APEMEM)會刊(2007-2008), pp. 37-43.
  2. U Seng Pan, R.P.Martins, J.E.Franca, “A 2.5V 320MSample/S SC Bandpass Multirate Filter for DDFS System in 0.35um CMOS,” in Proc. Symposium On Technological Innovation In Macau, Macau, China, Dec. 2002.
  3. U Seng Pan, R.P.Martins, J.E.Franca, “New Impulse Sampled Switched-Capacitor Interpolators” in Macau Engineering Bulletin, No. 3, Dec. 1996

Contact Details

Faculty of Science and Technology
University of Macau, E11
Avenida da Universidade, Taipa,
Macau, China

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Telephone: (853) 8822-4376
Fax: (853) 8397-8797
Email: benspu