Sai Weng SIN, Terry  冼世榮
Associate Professor
Associate Head of Department of Electrical and Computer Engineering (ECE)

Academic Qualifications | Professional Experience | Teaching Experience | Research | Professional Services - External | Professional Services - Internal | Professional Review Services | Honors and Awards | Student Honors and Awards under Advisory | Invited Talks | Scientific Publications | Professional Affiliations | Contact Details

Academic Qualifications
Professional Experience
Teaching Experience

B.Sc. Courses

  1. Analog Integrated Circuit Design (ELEC371)
  2. Signals and Systems (ECEB210 / ELEC261)
  3. System Design (ELEC437) / Design Project I (ECEB410)
  4. Project (ELEC402) / Design Project II (ECEB420)

M.Sc. Courses

  1. Advanced Topics in Analog and Mixed-Signal Integrated Circuits (IMSE022/ELCE722)
  2. Microelectronic Circuit Design (IMSE004)
  3. Microelectronic for Telecommunication and Signal Processing (IMSE011/ELCE711)
  4. Introduction to Research (IMSE001/ELCE701)
  5. Thesis (ELCE799)

Ph.D Courses

  1. Advanced Topics in Electrical and Computer Engineering (ELCE818)
  2. Microelectronics in Signal Processing and Communications (ELCE808)

Research

Research Interests

Thesis Co-Supervision

Ph.D Theses

  1. Sep 2014 – Present

Dongyang Jiang, Advanced Techniques for CMOS Sigma-Delta Modulators

  1. Sep 2014 – Present

Mingqiang Guo, Advanced Techniques for CMOS Pipelined Data Converters

  1. Sep 2014 – Present

Shasha Liu, Advanced Techniques for CMOS Pipelined Data Converters

  1. Sep 2013 – Present

Biao Wang, Incremental Oversampling Sigma-Delta Converters

  1. Sep 2012 – Present

Xing Dezhi, Advanced Techniques in Analog to Digital Converters

  1. Sep 2012 – Present

Jianwei Liu, Time-to-Digital Converter

  1. Sep 2011 – Present

Si-Seng Wong, Two-Step Binary Search Analog-to-Digital Converters

  1. Sep 2010 – Present

Feng Da, Hybrid Continuous- and Discrete-Time Sigma-Delta Modulator

  1. Sep 2010 – Present

Ding Li, Background Digital Calibration Techniques for High-Resolution Pipelined ADC

  1. Sep 2009 – Present

Zhong Jianyu, Digital Calibration Techniques in Split-SAR ADC

  1. Sep 2009 – Present

Arshad Hussain, The Design of Passive Sigma-Delta ADC

  1. Sep 2011 – Jul 2015

Chi-Hang Chan, Design Techniques and Considerations in Low to Moderate to Low Resolution Power efficient GHz Range ADCs

  1. Sep 2005 – Apr 2012

U-Fat Chio, Design Techniques for Low-Power High-Speed Analog-to-Digital Converters using Binary-Search and Subranging Schemes

M.Sc Theses

  1. Sep 2014 – Present

Jixuan Li, Power Efficient Techniques for Battery Management System

  1. Sep 2014 – Present

Hubert Liang, Low Power Sigma-Delta Modulator

  1. Sep 2013 – Present

Jiaji Mao, Low Power Pipelined Analog-to-Digital Converter

  1. Sep 2013 – Present

Dicky Fong, Hybrid Sigma-Delta Modulator 

  1. Sep 2012 – Present

Qi Liang, Discrete-Time MASH Sigma-Delta Modulator 

  1. Sep 2012 – Present

Qin Weiwei, Measurement Techniques for High-Performance Data Converters 

  1. Sep 2012 – Present

Yan Rongshen, On the Study of Advanced CMOS Operational Amplifiers

  1. Sep 2012 – Present

Li Wei, Data Converters for Navigation Systems

  1. Sep 2012 – Present

Ren Yuan, Analog Front-Ends Design for Integrated Power Electronics Controller

  1. Sep 2010 – Oct 2013

Yun Du, High-Performance Continuous-Time Sigma-Delta Modulator 

  1. Sep 2008 – Present

Chon-Hei Lei, Background Digital Calibration Techniques in High-Speed Pipelined Analog-to-Digital Converters for High Definition TV

  1. Sep 2006 – Mar 2015

Yuan Fei, A 10b Pipelined ADC with Nonlinear Digital Background Calibration & 2.5b/stage Opamp Sharing Architecture

  1. Sep 2010 – Jul 2013

Wenlan Wu, Monotonic Multi-Switching Method for
Ultra-Low-Voltage Energy Efficient SAR ADCs 

  1. Sep 2006 – Jul 2013

Cheok-Teng Lei, Applying the Novel High Speed Robust Level Converter to a 12-bit Successive Approximation Analog-to-Digital Converters with Dual Supply Domain

  1. Sep 2009 – Feb 2013

Cai Chenyan, Low Power High Efficiency Excess-Loop-Delay Compensation Techniques in Continuous-Time Delta-Sigma Modulators

  1. Sep 2009 – Jun 2012

Jiang Yang, On the Study of Clock-Jitter Insensitive Circuit Techniques in Continuous-Time Sigma-Delta Modulators

  1. Sep 2010 – May 2012

Peng Zhang, 时间交织型模数转换器时钟偏差校准技术研究(Joint-Supervision with Tsinghua University)

  1. Sep 2010 – May 2012

Zhijie Chen, 应用于生物医学领域的ΣΔ调制器低功耗研究(Joint-Supervision with Tsinghua University)

  1. Sep 2009 – May 2012

Rui Wang, 基于数字校准的流水线逐次逼近模数转换器的芯片实现 (Joint-Supervision with Tsinghua University)

  1. Sep 2009 – Dec 2011

Guohe Yin, 满足生物医学低功耗需求的模数转换器设计技术研究 (Joint-Supervision with Tsinghua University)

  1. Sep 2009 – Jul 2011

Chi-Hang Chan, A Study on Comparator and Offset Calibration Techniques in High Speed Nyquist ADCs

  1. Sep 2009 – Jul 2011

Si-Seng Wong, Design of Analog-to-Digital Converters with Binary Search Algorithm and Digital Calibration Techniques

  1. Sep 2008 – Aug 2010

Li Ding, Comprehensive Digital Calibration Techniques For High Resolution ADCs

  1. Sep 2007 – Aug 2010

Kim-Fai Wong, Speed Enhancement Techniques for Comparator-Based Switched-Capacitor Circuits

Bachelor Theses (12 Projects, 21 B.Sc students)

  1. Jul 2013 – Jun 2014

Jiang Dongyang, Liang Junhao, A 107 dB DR, 106dB SNDR Sigma-Delta ADC Using a Charge-Pump Integrator for Audio Application

  1. Jul 2013 – Jun 2014

Li Ji Xuan, Zeng Wen Liang, Power Efficient and Fast Charger Techniques Applied for Battery Management System

  1. Jul 2012 – Jun 2013

Fong Tek Kei, A 103dB Dynamic Range, 106dB SNDR Sigma-Delta ADC for Audio Applications

  1. Jul 2012 – Jun 2013

Bai Ziwen, A Micropower Management System for Photovoltaic Cells with Maximum Output Power Control

  1. Jul 2011 – Jun 2012

Zhou Tianxiang, A Multibit Dual-Feedback CT Sigma Delta Modulator with Lowpass Signal Transfer Function

  1. Jul 2011 – Jun 2012

Cheng Xiaojing, Ding Shixuan, Wideband Time-Interleaved Pipelined ADC using LMS Timing-Skew Calibration Engine for a 4G LTE Smartphone

  1. Jul 2010 – Jun 2011

Yan Pengyu, Chen Zhiyuan, A 13-bit 64 MS/s Digital Enhanced Pipelined ADC for 4G LTE Application

  1. Jul 2009 – Jun 2010

Du Yun, He Tao, A 65nm CMOS High-Speed Low-Power Continuous-Time Sigma-Delta Modulator with VCO-Based Quantizer for WiMAX Application

  1. Jul 2008 – Jun 2009

Jiang Yang, Yu Xiaofeng, Cai Chenyan, A 65nm CMOS High-Speed Low-Power Continuous-Time Sigma-Delta Modulator For 3G WCDMA Receivers

  1. Jul 2008 – Jun 2009

Fan Wa Pan, Chio Chan Keong, A 1-V 12-bit 200-MS/s Pipelined ADC with Digital Signal-Dependant Dithering Calibration for HDTV Video Analog Frond-End

  1. Jul 2007 – Jun 2008

Chon-Hei Lei, Background Digital Calibration for Full HD(High-Definition) Video Analog Front-End

  1. Jul 2007 – Jun 2008

Sio Chan and Li Ding, Low-Power High-Speed Comparator-Based Pipeline ADC for Portable Wireless Devices

  1. Jul 2007 – Jun 2008

Wai-Hou Chan and Li Xie, A 10-bit 60-MS/s Asynchronous Charge-Sharing SAR ADC in 90-nm CMOS for Mobile TV Applications

  1. Jul 2007 – Jun 2008

Yin-Sheng Zhao and Seng-Cheong Chao, Comparator-Based Multi-mode Sigma Delta Modulator for 3G Analog Front-End

  1. Jul 2007 – Jun 2008

Po-Lap Chan and Ka-Cheong Lao, Study of Low Drop-Out Regulators for Power Management in Portable Devices

Funded Research Projects

Industrial Engineering Projects


Professional Services - External
Professional Services - Internal
Professional Review Services
Honors and Awards
Student Honors and Awards under Advisory
Invited Talks
  1. “Macao Chip by Macao People" - Sharing Session on the First State Scientific and Technological Progress Award for Macao澳門人, 澳門” – 澳門首獲國家科學技術進步獎成果分享, Feb. 2012.
  2. “Research and Future Perspective of Data Converters Research”, Academic Committee Meeting, State-Key Laboratory of Analog and Mixed-Signal VLSI, Mar. 2012.
  3.  “Design Techniques for Nanometer Data Converters,” Institute of Superior Technico (IST), Lisboa, Portugal, Mar. 2012.
  4.  “Design Techniques for Nanometer Data Converters,” The New University of Lisbon, Lisboa, Portugal, Mar. 2012.
  5. “High-Speed, High-Resolution, Low-Power Analog-to-Digital Conversion System with Emerging Scaled CMOS Technology”, FDCT Project Presentation, Macau Science and Technology Development Fund, Nov. 2011.
  6.  “Design Techniques for Nanometer Data Converters,” Hong Kong University of Science and Technology, Hong Kong, Dec. 2010.
  7. “Macau Microelectronics Development – Histories and Prospects” University of Macau, Macau, Oct. 2009 and Nov 2010.
  8.  “Introduction to the Research in Data Conversion and Signal Processing Research Line at University of Macau,” Tsinghua University, Shenzhen, Nov 2009.
  9.  “Introduction to the Research in Data Conversion and Signal Processing Research Line at University of Macau,” Fudan University, Shanghai, May 2009.

Scientific Publications

Book

  1. Sai-Weng Sin, Seng-Pan U, and R.P.Martins, “Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters, Analog Circuits and Signal Processing, Springer,  Oct. 2010.
    Printed version:     (ISBN: 978-90-481-9709-5)
    e-Book:   (ISBN: 978-90-481-9710-1)
    Link: http://www.springer.com/engineering/electronics/book/978-90-481-9709-5

Patents

  1. Sai-Weng Sin, Li Ding, Yan Zhu, He-Gong Wei, Chi-Hang Chan, U-Fat Chio, Seng-Pan U, R.P.Martins, F.Maloberti, “Time-Interleaved Pipelined-SAR Analog to Digital Converter with Low  Power Consumption,” US Patent, No. 8,427,355, from 23rd Apr, 2013.
  2. Sai-Weng Sin, Li Ding, Yan Zhu, He-Gong Wei, Chi-Hang Chan, U-Fat Chio, Seng-Pan U, R.P.Martins, F.Maloberti, “Analog to Digital Converter Circuit(類比至數位轉換器電路),” Taiwan Patent, No. 201242261, Mar 2014.
  3. Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P. Martins and Franco Maloberti, “N-Bits Successive Approximation Register Analog-to-Digital Converter Circuit,” US PatentNo: 8,344,931, from 1th Jan, 2013.
  4. He-Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “Delay Generator,” US patent, No. US8,411,259 B2, May 2013.
  5. U-Fat Chio, He-Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R. P. Martins and Franco Maloberti, “Analog-to-Digital Converting System (類比數位轉換系統),” Taiwan Patent Application No: 100103984, 2011.
  6. He-Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “Delay Generator (延遲產生器),” Taiwan Patent,  No. 201246793, Mar 2014.
  7. U-Fat Chio, He-Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R. P. Martins and Franco Maloberti, “Cascade Analog to Digital Converting System,” US Patent, No. 8,466,823 B2, 2nd Aug, 2012.
  8. Chi-Hang Chan, Yan Zhu, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R. P. Martins “Comparator and Calibration Thereof,” US Patent, No. 13/675311, Jul 2014.

Journal Papers

IEEE Journal of Solid-State Circuits (JSSC)
  1. Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti, "A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65-nm CMOS", IEEE Journal of Solid-State Circuits. vol. 48, Issue 9, pp. 2154-2169, Sept 2013. [SCI, EI]
    [Ranked 12th Top Aceess paper in IEEE Journal of Solid-State Circuits in Aug 2013 with it Early Access Version]
  2. Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, "A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC", in press in IEEE Journal of Solid-State Circuits. vol. 48, Issue 8, pp. 1783-1794, Aug 2013. [SCI, EI]
    [Ranked 3rd Top Access paper in IEEE Journal of Solid-State Circuits in Jul 2013 with it Early Access Version]
    [Ranked 95th Top Access paper in the whole IEEE Xplore datebase in Jul 2013 with it Early Access Version]
  3. He-Gong Wei, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti, "A 8-bit 400MS/s 2-bit per cycle SAR ADC with Resistive DAC", IEEE Journal of Solid-State Circuits, vol. 47, Issue 11, pp. 2763-2772, Nov 2012. [SCI, EI]
    [Ranked 78th Top Access paper in the whole IEEE Xplore datebase in Nov 2012]
  4. Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "A 50fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation", IEEE Journal of Solid-State Circuits, vol. 47, Issue 11, pp. 2614 – 2626, Nov 2012. [SCI, EI]
    [Ranked 43th Top Access paper in the whole IEEE Xplore datebase in Nov 2012]
  5. Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P. Martins and Franco Maloberti, " A 10-bit 100-MS/s Reference-Free SAR ADC in 90nm CMOS,” in IEEE Journal of Solid-State Circuits, vol. 45, no. 6, pp. 1111 – 1121, Jun 2010. [SCI, EI]
IEEE Transactions on Circuits and Systems I - Regular Papers (TCAS-I)
  1. Sai-Weng Sin, Seng-Pan U, and R.P.Martins, “Generalized Circuit Techniques for Low-Voltage High-Speed Reset- and Switched-Opamps,” in IEEE Transactions on Circuits and Systems I - Regular Papers, vol. 55, no. 8, pp. 2188-2201, Sep 2008. [SCI, EI]
IEEE Transactions on Circuits and Systems II - Express Briefs (TCAS-II)
  1. U-Fat Chio, He-Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti “Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC”in IEEE Transactions on CAS – Part II: Express Briefs, vol.57, issue8,pp607-611, Aug 2010 [SCI, EI]
  2. U-Fat Chio, He-Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R. P. Martins and Franco Maloberti, “Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC,” in press in IEEE Trans. On Circuits and System II – Express Briefs, vol. 57, no. 8, pp. 607 – 611, Aug 2010 [SCI, EI]
  3. He-Gong Wei, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “A Rapid Power-Switchable Track-and-Hold Amplifier in 90nm CMOS,” in IEEE Trans. On Circuits and System II – Express Briefs, vol. 57, no. 1, pp. 16-20, Jan 2010. [SCI, EI]
  4. Sai-Weng Sin, U-Fat Chio, Seng-Pan U and R. P. Martins, “Statistical Spectra and Distortion Analysis of Time-Interleaved Sampling Bandwidth Mismatch,” in IEEE Trans. on Circuits and Systems II – Express Briefs, vol. 55, no. 7, pp. 648 – 652, Jul 2008. [SCI, EI]
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)
  1. Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti, “Split-SAR ADCs: Improved Linearity with Power and Speed Optimization in 90nm CMOS,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 2, pp. 372-383, Feb. 2014.
IEEE Transactions on Power Electronics (TPEL)
  1. Man-Chung Wong, Yan-Zheng Yang, Chi-Seng Lam, Wai-Hei Choi, Ning Yi Dai, Yajie Wu, Chi-Kong Wong, Sai-Weng Sin, U-Fat Chio, Seng-Pan, U, R.P.Martins, “Self-Reconfiguration Property of a Mixed Signal Controller for Improving Power Quality Compensation During Light Loading,” in IEEE Trans. on Power Electronics, vol. 30, no. 10, pp. 5938 – 5951, Oct 2014.
IEEE Transactions on Instrumentation and Measurement (TIM)
  1. Seng-Pan U, Sai-Weng Sin and R.P.Martins, “Exact spectra analysis of sampled signal with jitter-induced nonuniformly holding effects,” in IEEE Trans. on Instrumentation and Measurement, vol. 53, no. 4, pp. 1279 – 1288, Aug 2004. [SCI, EI]
Other Journals
  1. Qi Liang, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, " Resolution-enhanced sturdy MASH delta–sigma modulator for wideband low-voltage applications", IET Electronics Letter, vol. 51, Issue 14, pp. 1061-1063, Jul. 2015.
  2. Chen-Yan Cai, Yang Jiang, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, "Excess-loop-delay compensation technique for CT ΔΣ modulator with hybrid active-passive loop-filters", Analog Integrated Circuits and Signal Processing, Springer, vol. 76, Issue 1, pp. 35-46, Jul. 2013.
  3. Yan Zhu, U-Fat Chio, He-Gong Wei, Sai-Weng Sin, Seng-Pan U and R.P. Martins, " Linearity Analysis On A Series-Split Capacitor Array for High-Speed SAR ADCs,” in Hindawi VLSI Design, Special Issue "Selected Papers from the Midwest Symposium on Circuits and Systems", vol. 2010, no. 1, pp. 1-8, Apr 2010.
  4. Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A 1.2-V 10-bit 60-360MS/s Time-Interleaved Pipelined ADC in 0.18um CMOS with Minimized Supply Headroom”, in IET Proceedings - Circuits, Devices and Systems,vol. 4, no. 1, pp. 1-13, Jan 2010.
  5. Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A 1-V 10b 40MS/s Pipelined ADC with Low-Voltage Circuit Techniques in 0.18um CMOS”, 澳門機電工程專業協會(APEMEM)會刊(2007-2008), pp. 37-43.

Conference Papers

IEEE International Solid-State Circuit Conference (ISSCC)
  1. He-Gong Wei, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R. P. Martins and F. Maloberti, “A 0.024mm2 8-bit 400 MS/s SAR ADC with 2-bit per Cycle and Resistive DAC in 65 nm CMOS,” in IEEE International Solid-State Circuit Conference (ISSCC),  vol. 54, pp.188-189, Feb 2011. (ISSCC Silk Road Award)
  2. Chi-Hang Chan*, Yan Zhu*, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “A 5.5mW 6b 5GS/s 4-times Interleaved 3b/cycle SAR ADC in 65nm CMOS,” in IEEE International Solid-State Circuit Conference (ISSCC), 2015.
  3. Yan Lu, Junmin Jiang, Wing-Hung Ki, C. Patrick Yue, Sai-Weng Sin,  Seng-Pan U, R. P. Martins, “A 123-Phase DC-DC Converter-Ring with Fast-DVS for Microprocessors,” in IEEE International Solid-State Circuit Conference (ISSCC), 2015.
IEEE International Symposium on VLSI Circuits (VLSI)
  1. Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A 34fJ 10b 500 MS/s Partial-Interleaving Pipelined SAR ADC,” 2012 Symposium on VLSI Circuits Digest of Technical Papers, page 90-91;13-15 June 2012, pp. 90-91, Jun 2012
  2. Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A 3.8mW 8b 1GS/s 2b/cycle Interleaving SAR ADC with Compact DAC Structure,” 2012 Symposium on VLSI Circuits Digest of Technical Papers, page 86-87, Hawaii,Jun 2012. (with Travel Grant Award)
IEEE Custom Integrated Circuits Conference (CICC)
  1. Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A 2.3mW 10-bit 170MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC,” in Proc. of IEEE Custom Integrated Circuits Conference – CICC, Sept 2012.
IEEE European Solid-State Circuits Conference (ESSCIRC)
  1. Rui Wang, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Zhihua Wang, Rui Paulo Martins, " A 12-Bit 110MS/S 4-Stage Single-Opamp Pipelined SAR ADC with Ratio-Based GEC Technique", to appear soon in Proc. IEEE European Solid-State Circuits Conference – ESSCIRC 2012, France, September 2012.
  2. Guohe Yin, He-Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Zhihua Wang, Rui Paulo Martins, A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS ", to appear soon in Proc. IEEE European Solid-State Circuits Conference – ESSCIRC 2012, France, September 2012.
  3. U-Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, " A 7-bit 300-MS/s Subranging ADC with Embedded Threshold & Gain-Loss Calibration", in Proc. IEEE European Solid-State Circuits Conference – ESSCIRC, pp. 363-366, Sept 2011.
  4. Sai-Weng Sin, Li Ding, Yan Zhu, He-Gong Wei, Chi-Hang Chan, U-Fat Chio, Seng-Pan U, R.P.Martins and F. Maloberti, "An 11b 60MS/S 2.1mW Two-Step Time-Interleaved SAR-ADC with Reused S&H", in Proc. IEEE European Solid-State Circuits Conference – ESSCIRC, pp. 218 - 221, Sept 2010.
IEEE Asian Solid-State Circuits Conference (A-SSCC)
  1. Li Ding, Wenlan Wu, Sai-Weng Sin, Seng-Pan, U, R.P.Martins, " A 13-bit 60MS/s split pipelined ADC with background gain and mismatch error calibration ", IEEE Asian Solid-State Circuit Conference – (A-SSCC), pp. 77-80, Nov 2013
  2. Jianyu Zhong, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R. P. Martins, "Inter-Stage Gain Error Self-Calibration of a 31.5fJ 10b 470MS/s Pipelined-SAR ADC", IEEE Asian Solid-State Circuit Conference – (A-SSCC), pp. 153-156, Nov 2012
  3. Zhijie Chen, Yang Jiang, Chenyan Cai, He-Gong Wei, Sai-Wen Sin, Seng-Peng U, Zhihua Wang, R. P. Martins, "A 22.4μW 80dB SNDR ΣΔ Modulator with Passive Analog Adder and SAR Quantizer for EMG Application", IEEE Asian Solid-State Circuit Conference – (A-SSCC), pp. 257-260, Nov 2012
  4. Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, R.P.Martins, Franco Maloberti, “A 35 fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation,” in IEEE Asian Solid-State Circuit Conference – A-SSCC, pp. 61-64, Nov 2011. (Student Design Contest Winner)
  5. Chi-Hang Chan, Yan Zhu, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A Reconfigurable Low-Noise Dynamic Comparator with Offset Calibration in 90nm CMOS,” in press in IEEE Asian Solid-State Circuit Conference – A-SSCC, pp. 233-236, Nov 2011.
  6. Si-Seng Wong, U-Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A 4.8-bit ENOB 5-bit 500MS/s Binary-Search ADC with Minimized Number of Comparators,” in IEEE Asian Solid-State Circuit Conference – A-SSCC, pp. 73-76, Nov 2011.
  7. He-Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A Process-insensitive Current-Controlled Delay Generator with Threshold Voltage Compensation,” in IEEE Asian Solid-State Circuit Conference (A-SSCC),  pp. 221-224, Nov, 2010.
  8. Sai-Weng Sin, He-Gong Wei, U-Fat Chio, Yan Zhu, Seng-Pan U, R.P. Martins and Franco Maloberti, " On-Chip Small Capacitor Mismatches Measurement Technique using Beta-Multiplier-Biased Ring Oscillator,” in Proc. of 2009 IEEE Asian Solid-State Circuit Conference (A-SSCC), pp. 49-52, Nov 2009.
IEEE International Symposium on Circuits and Systems (ISCAS)
  1. Da Feng, F.Maloberti, Sai-Weng Sin, Seng-Pan U and R.P.Martins, " Jitter-resistant Capacitor Based Sine-Shaped DAC for Continuous-Time Sigma-Delta modulators ", IEEE International Symposium on Circuits and Systems (ISCAS),  May 2014.
  2. Wen-Lan Wu, Yan Zhu, U-Fat Chio, Li Ding, Chi-Hang Chan, Sai-Weng Sin,  Seng-Pan U,  Rui Paulo Martins, "A 0.6V 8b 100MS/s SAR ADC with Minimized DAC Capacitance and Switching Energy in 65nm CMOS", IEEE International Symposium on Circuits and Systems (ISCAS),  May 2013.
  3. Yun Du, Tao He,  Yang Jiang, Sai-Weng Sin,  Seng-Pan U,  Rui Paulo Martins, "A Continuous-Time VCO-Assisted VCO-Based Sigma Delta Modulator with 76.6dB SNDR and 10MHz BW", IEEE International Symposium on Circuits and Systems (ISCAS), pp. May 2013.
  4. Tao He, Yang Jiang, Yun Du, Sai-Weng Sin, Seng-Pan U and Rui. P. Martins, “A 10MHz BW 78dB DR CT ΣΔ Modulator with Novel Switched High Linearity VCO-Based Quantizer,” in 2012 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 65-69, May. 2012.
  5. Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, “A Voltage Feedback Charge Compensation Technique for Split DAC Architecture in SAR ADCs”, in 2010 IEEE International Symposium on Circuits and Systems (ISCAS). pp. 607-611, May. 2010.
  6. He-Gong Wei, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U and R.P. Martins, “A Power Scalable 6-bit 1.2GS/s Flash ADC with Power on/off Track-and-Hold and Preamplifier”, in Proc. of 2008 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 5-8, Seattle, USA, May 2008.
  7. Sai-Weng Sin, Seng-Pan U and R. P. Martins, “A novel low-voltage finite-gain compensation technique for high-speed reset- and switched-opamp circuits,” in Proceedings of 2006 IEEE International Symposium on Circuits and Systems - ISCAS'2006, p. 3794-3797, May 2006.
  8. Jun-Xia Ma, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “A Power-Efficient 1.056 GS/s Resolution-Switchable 5-bit/6-bit Flash ADC for UWB Applications,” in Proceedings of 2006 IEEE International Symposium on Circuits and Systems - ISCAS'2006, p. 4305-4308, May 2006.
  9. Sai-Weng Sin, Seng-Pan U, and R.P.Martins, "A Novel Low-Voltage Cross-Coupled Passive Sampling Branch for Reset- and Switched-Opamp Circuits,” in Proceedings of 2005 IEEE International Symposium on Circuits and Systems - ISCAS'2005,p. 1585-1588, May 2005.
  10. Sai-Weng Sin, Seng-Pan U, and R.P.Martins, "A Novel Very Low-Voltage SC-CMFB Technique for Fully-Differential Reset-Opamp Circuits,” in Proceedings of 2005 IEEE International Symposium on Circuits and Systems - ISCAS'2005,p. 1581-1584, May 2005.
  11. Sai-Weng Sin, Seng-Pan U, and R.P.Martins, " A Generalized Timing-Skew-Free, Multi-Phase Clock Generation Platform for Parallel Sampled-Data Systems,” in Proceedings of 2004 IEEE International Symposium on Circuits and Systems - ISCAS'2004, vol.1, pp. I-369 – I-372 , May 2004.
  12. Sai-Weng Sin, Seng-Pan U, and R.P.Martins, " Timing-Mismatch Analysis in High-Speed Analog Front-End with Nonuniformly Holding Output,” in Proceedings of IEEE International Symposium on Circuits and Systems 2003 - ISCAS'2003, vol. 1, pp. I-129 – I-132, May 2003.
IEEE International Conference on Acoustics, Speech & Signal Processing (ICASSP)
  1. Sai-Weng Sin, Seng-Pan U and R.P.Martins, "Quantitative Noise Analysis of Jitter-Induced Non-Uniformly Sampled-And-Held Signals," in Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing – “ICASSP'2003", vol. 6, pp. VI-253 - 256, April 2003.
IEEE International Solid-State CircuiIEEE Instrumentation and Measurement Technology Conference (IMTC)
  1. Seng-Pan U, Sai-Weng Sin and R.P.Martins, " Spectra Analysis of Nonuniformly Holding Signals for Time-Interleaved Systems with Timing Mismatches," in Proceedings of IEEE Instrumentation and Measurement Technology Conference - IMTC'2003, vol. 2, pp. 1298-1301, May 2003.
IEEE Midwest Symposium on Circuits and Systems (MWSCAS)
  1. Ding Li, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, "A Background Gain-Calibration Technique for Low Voltage Pipelined ADCs Based on Nonlinear Interpolation", in press in IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS), Aug. 2013.
  2. Chen-Yan Cai, Yang Jiang, Sai-Weng Sin, Seng-Pan U and Rui. P. Martins, “An ELD Tracking Compensation Technique for Active-RC CT ΣΔ Modulators,” in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS, pp. 1096 – 1099, Aug 2012.
  3. Zhong Jian Yu, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R.P.Martins, "A Multi-Merged-Switched Redundant Capacitive DACs for 2b/cycle SAR ADC", IEEE Midwest Symposium on Circuits and Systems – MWSCAS, Aug. 2011
  4. Chen-Yan Cai, Yang Jiang, Sai-Weng Sin, Seng-Pan U and Rui. P. Martins, “A Passive Excess-Loop-Delay Compensation Technique for Gm-C Based Continuous-Time ΣΔ Modulators,” IEEE Midwest Symposium on Circuits and Systems – MWSCAS, Aug. 2011.
  5. Yang Jiang, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U and Rui P. Martins, “Clock-Jitter Sensitivity Reduction in CT ΣΔ Modulators Using Voltage-Crossing Detection DAC,” IEEE Midwest Symposium on Circuits and Systems – MWSCAS, Aug. 2011
  6. Tao He, Yun Du, Yang Jiang, Sai-Weng Sin, Seng-Pan U and Rui P. Martins, “A Dual-VCO-Based Quantizer with Highly Improved Linearity and Enlarged Dynamic Range,” IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2011, Aug. 2011.
  7. Peng Zhang, Zhijie Chen, He-Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Zhihua Wang, “A Charge Pump Based Timing-Skew Calibration for Time-Interleaved ADC,” IEEE Midwest Symposium on Circuits and Systems – MWSCAS, Aug. 2011.
  8. Zhijie Chen, Peng Zhang, Hegong Wei, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Zhihua Wang, “Noise Shaping Implementation in Two-Step/SAR ADC Architectures Based on Delayed Quantization Error,” IEEE Midwest Symposium on Circuits and Systems – MWSCAS, Aug. 2011.
  9. Jianyu Zhong, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, “A Multi-Merged-Switched Redundant Capcitive DACs for 2b/cycle SAR ADC,” IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2011, Aug 2011.
  10. Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A Threshold-Embedded Offset Calibration Technique for Inverter-Based Flash ADCs,”  IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010, pp. 489-492, Aug. 2010.
  11. Kim-Fai Wong, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “Level-Shifting Variable Current Charging Technique for High-Speed Comparator-Based Switched-Capacitor Circuits,” Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010, pp. 566-569, Aug. 2010.
  12. Si-Seng Wong, U-Fat Chio, Hou-Lon Choi, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A Power Effective 5-bit 600 MS/s Binary-Search ADC with Simplified Switching,” in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010, pp. 29-32, Aug. 2010.
  13. Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “Parasitics Nonlinearity Cancellation Technique for Split DAC Architecture by Using Capacitive Charge-Pump,” in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010, pp. 889-892, Aug. 2010.
  14. Kim-Fai Wong, Sai-Weng Sin, Seng-Pan U and R.P. Martins, " A Modified Charging Algorithm for Comparator-Based Switched-Capacitor Circuits,” in Proc. of 2009 Midwest Symposium on Circuits and Systems (MWSCAS), pp. 86-89, Aug. 2009.
  15. Yan Zhu, U-Fat Chio, He-Gong Wei, Sai-Weng Sin, Seng-Pan U and R.P. Martins, " Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs,” in Proc. of 2008 Midwest Symposium on Circuits and Systems (MWSCAS), pp. 922-925, Aug 2008 .
IEEE International Conference on Electronics, Circuits and Systems (ICECS)
  1. Yang Jiang, Kim-Fai Wong, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “A Fixed-Pulse Shape Feedback Technique with reduced clock-jitter sensitivity in Continuous-Time sigma-delta modulators” in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 547-550, Dec, 2010.
  2. Guohe Yin, U-Fat Chio, He-Gong Wei, Sai-Weng Sin, Seng-Pan U, R.P. Martins, Zhihua Wang, “An Ultra Low Power 9-bit 1-MS/s Pipelined SAR ADC for Bio-medical Applications” in Proc. of IEEE International Conference on Electronics, Circuits an d Systems (ICECS), pp. 878-881, Dec, 2010.
  3. Yan Zhu, U-Fat Chio, He-Gong Wei, Sai-Weng Sin, Seng-Pan U and R.P. Martins, "A Power-Efficient Capacitor Structure for High-Speed Charge Recycling SAR ADCs,” in Proc. of 2008 IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 642-645, Aug 2008.
IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS)
  1. Yun Du, Tao He, Yang Jiang, Sai-Weng Sin, Seng-Pan U, R. P. Martins, "A Robust NTF Zero Optimization Technique for Both Low and High OSRs Sigma-Delta Modulators", IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2012, pp. 29-32, 2012
  2. Tao He, Yun Du, Yang Jiang, Sai-Weng Sin, Seng-Pan U, R. P. Martins, "A DT 0-2 MASH Modulator with VCO-Based Quantizer for Enhanced Linearity,", IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2012, pp. 33-36, 2012
  3. Wen-Lan Wu, Sai-Weng Sin, Seng-Pan U, R. P. Martins, "A 10-bit SAR ADC With Two Redundant Decisions and Splitted-MSB-Cap DAC Array", IEEE ASIA Pacific Conference on Circuits and system (APCCAS), 2012
  4. Yang Jiang, Kim-Fai Wong, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “A Reduced Jitter-Sensitivity Clock Generation Technique for Continuous-Time ΣΔ Modulators,” in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 1011-1014, Dec. 2010.
  5. Li Ding, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “An Efficient DAC and Interstage Gain Error Calibration Technique For Multi-Bit Pipelined ADCs” in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 208-211, Dec. 2010.
  6. He-Gong Wei, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U and R.P. Martins, " A Process- and Temperature- insensitive Current-Controlled Delay Generator for Sampled-Data Systems,” in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 1192-1195, Dec. 2008.
  7. U-Fat Chio, He-Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U and R.P. Martins, " A Self-Timing Switch-Driving Register by Precharge-Evaluate Logic for High-Speed SAR ADCs” in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 1164-1167, Dec. 2008.
  8. Li Ding, Sio Chan, Kim-Fai Wong, Sai-Weng Sin, Seng-Pan U and R.P. Martins, " A Pseudo-Differential Comparator-Based Pipelined ADC with Common Mode Feed Forward Technique” in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 276-279, Dec. 2008.
IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)
  1. Seng-Pan U, Sai-Weng Sin, Yan Zhu, U-Fat Chio, He-Gong Wei and, R. P. Martins, " Design Techniques for Nanometer Wideband Power-Efficient CMOS ADCs,” in Proc. of Proc. of IEEE International Symposium on Radio-Frequency Integration Technology – RFIT’2011, pp. 173-176, Nov 2011.
IEEE International SoC Design Conference (ISOCC)
  1. Arshad Hussain, Sai-Weng Sin, Seng-Pan U and Rui P. Martins, “Hybrid Loopfilter Sigma-Delta Modulator With NTF Zero Compensation,” in International SoC Design Conference – ISOCC, pp. 76-79, Nov 2011.
  2. Si-Seng Wong, Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “Parasitic Calibration by Two-Step Ratio Approaching Techinque for Split Capacitor Array SAR ADCs,in Proc. of 2009 International SoC Design Conference (ISOCC), invited, pp. 333-336, Nov. 2009.
  3. Chi-Hang Chan, Yan Zhu, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P.Martins,A Voltage-Controlled Capacitance Offset Calibration Technique for High Resolution Dynamic Comparator,in Proc. of 2009 International SoC Design Conference (ISOCC), invited, pp. 392-395, Nov. 2009.
Other International Conferences
  1. Haojuan Dai, Yan Lu, Man-Kay Law, Sai-Weng Sin, Seng-Pan, U, R.P.Martins, “A review and design of the on-chip rectifiers for RF energy harvesting,” in IEEE International Wireless Symposium, Mar 2015.
  2. Da Feng, Sai-Weng Sin, E. Bonizzoni, F.Maloberti, “Time interleaved current steering DAC for ultra-high conversion rate,” in IEEE Ph.D Research in Micro-electronics & Electronics (PRIME), Jun 2014.
  3. Arshad Hussain, Sai-Weng Sin, Seng-Pan U and Rui P. Martins, “NTF Zero Compensation Technique For Passive Sigma-Delta Modulator,” in IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), pp. 82-85, Oct 2011.
  4. Yuan Fei, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “A Nonlinearity Digital Background Calibration Algorithm for 2.5bit/stage Pipelined ADCs With Opamp Sharing Architecture,” in IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), pp. 1-4, Oct 2011.
  5. Rui Wang, U-Fat Chio, Chi-Hang Chan, Li Ding, Sai-Weng Sin, Seng-Pan U, Zhihua Wang and R. P. Martins, “A time-efficient dither-injection scheme for pipelined SAR ADC,” in IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), pp. 9-12, Oct 2011.
  6. Bo Sun; U-Fat Chio; Chi-Seng Lam; Ning-Yi Dai; Man-Chung Wong; Chi-Kong Wong; Sai-Weng Sin; Seng-Pan U; R. P. Martins, “A FPGA-Based Power Electronics Controller for Hybrid Active Power Filters,” in IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), pp. 25-28, Oct 2011.
  7. Bo Sun; Ning-Yi Dai; U-Fat Chio; Man-Chung Wong; Chi-Kong Wong; Sai-Weng Sin; Seng-Pan U; R. P. Martins, "FPGA-based Decoupled Double Synchronous Reference Frame PLL for Active Power Filters", 2011 6th IEEE Conference on Industrial Electronics and Applications (ICIEA), pp. 2145 – 2150, 2011.
  8. Yuan Fei, Sai-Weng Sin, Seng-Pan U and R. P. Martins, “A Digital Background Nonlinearity Calibration Algorithm for Pipelined ADCs,” IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), pp. 115-118, Sep 2010.
  9. Li Ding, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A Noise-Insensitive Offset Calibration Technique for Time Interleaved SAR ADC”, accepted in2010 IEEE Latin-American Symposium on Circuits and Systems (LASCAS).
  10. Li Ding, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “A Background Amplifier Offset Calibration Technique for High Resolution Pipelined ADC”, in 2010 IEEE International NEWCAS Conference, pp. 41-44, Jun. 2010.
  11. U-Fat Chio, Hou-Lon Choi, Chi-Hang Chan, Si-Seng Wong, Sai-Weng Sin, Seng-Pan U, R. P. Martins, “Comparator-Based Successive Folding ADC,” IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), pp. 117-120, Nov. 2009. (Bronze Leaf Certificate)
  12. Sai-Weng Sin, Seng-Pan U and R.P.Martins, “Novel Timing-Skew-Insensitive, Multi-phase Clock Generation Scheme for Parallel DAC and N-Path Filter”, in Proceedings of RIUPEEEC, pp.133-136, Macao, China, July 2006. (Paper with Certificate of Merit)
  13. Jun-Xia Ma, Sai-Weng Sin, Seng-Pan U, and R.P.Martins, “A 1.8V 1.056GS/s 6-b Flash-Interpolation ADC for MB-OFDM UWB Applications”, in Proceedings of RIUPEEEC, pp.105-108, Macao, China, July 2006.
  14. Sai-Weng Sin, Seng-Pan U, and R.P.Martins, “Novel Low-Voltage Circuit Techniques for Fully-Differential Reset- and Switched-Opamps,” in Proceedings of PRIME'2005,vol. 2, p. 398-401,  July 2005.
  15. Sai-Weng Sin, Seng-Pan U and R.P.Martins, “Novel low jitter multi-phase clock generation scheme for parallel analog-to-digital conversion systems,”in Proceedings of 2004 IEEJ International Analog VLSI  Workshop, vol.1, pp. 172 – 175 , Oct 2004.
  16. Sin Sai Weng, Lai Keng Chong, Chiang Kuok Vai, Choi Wai Wa, K.W.Tam and R.P.Martins, "An analytical linearization method for CMOS MMIC power amplifier using Multiple Gated Transistors," in Proceedings of IEEE International Conference on ASIC - ASICON’2001, pp.670-672, Oct. 2001.
  17. Sin Sai Weng, Lai Keng Chong, Chiang Kuok Vai, Choi Wai Wa, K. W. Tam and R. P. Martins, “A New IMD3 Reduction Approach based on Composite Effect of g"m and g"ds,” in Proceedings of IEEE CAS Workshop on Wireless Communications and Networking, South Bend, Indiana, USA, Aug., 2001.

Professional Affiliations
Contact Details

Faculty of Science and Technology
University of Macau, E11
Avenida da Universidade, Taipa,
Macau, China

Room: E11-3049
Telephone: (853) 8822-8795
Fax: (853) 8397-8797
Email: terryssw